# US 10,483,243 B2 · Semiconductor devices including stacked semiconductor chips

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- Number: US 10,483,243 B2
- Document ID: US10483243B2
- Status: Granted
- Kind: B2
- Application number: 16/236,882
- Filed: 2018-12-31
- Published: 2019-05-23
- Granted: 2019-11-19
- Earliest claimed: 2015-11-27
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Donghyun Kim; DooWon Kwon
- Web page: https://patentgrep.com/patent/US10483243B2

## CPC

- H10W 90/00: Package configurations
- B60H 1/00764: {the input being a vehicle driving condition, e.g. speed (B60H1/00828, B60H1/00864 take precedence)}
- B60H 1/00828: {Ventilators, e.g. speed control (B60H1/00864 takes precedence)}
- B60H 1/321: {for preventing the freezing of a heat exchanger}
- B60K 11/06: with air cooling
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10F 39/199: {Back-illuminated image sensors}
- H10F 39/809: {of hybrid image sensors}
- H10F 39/811: {Interconnections}
- B60H 2001/3248: {related to pressure}
- B60H 2001/3258: {of the air at a condensing unit}
- F01P 7/048: {using electrical drives}
- F01P 11/20: concerning atmospheric freezing conditions, e.g. automatically draining or heating during frosty weather
- F01P 2050/24: Hybrid vehicles
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/856: {Bump connectors and die-attach connectors (bumps embedded in underfills H10W74/15)}
- H10W 90/20: Configurations of stacked chips
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B60H: ARRANGEMENTS OF HEATING, COOLING, VENTILATING OR OTHER AIR-TREATING DEVICES SPECIALLY ADAPTED FOR PASSENGER OR GOODS SPACES OF VEHICLES
- B60K: ARRANGEMENT OR MOUNTING OF PROPULSION UNITS OR OF TRANSMISSIONS IN VEHICLES; ARRANGEMENT OR MOUNTING OF PLURAL DIVERSE PRIME-MOVERS IN VEHICLES; AUXILIARY DRIVES FOR VEHICLES; INSTRUMENTATION OR DASHBOARDS FOR VEHICLES; ARRANGEMENTS IN CONNECTION WITH COOLING, AIR INTAKE, GAS EXHAUST OR FUEL SUPPLY OF PROPULSION UNITS IN VEHICLES
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- F01P: COOLING OF MACHINES OR ENGINES IN GENERAL; COOLING OF INTERNAL-COMBUSTION ENGINES (arrangements in connection with cooling of propulsion units in vehicles B60K11/00; heat-transfer, heat-exchange or heat-storage materials C09K5/00; {cooling of gas-turbine engines F02C7/12}; heat exchange in general, radiators F28)

## Abstract

A semiconductor device includes a chip stack structure including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer disposed on the first circuit layer and including a first metal pad electrically connected to the first circuit layer. The second semiconductor chip includes a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer disposed on the second circuit layer and including a second metal pad electrically connected to the second circuit layer. The first connecting layer faces the second connecting layer. The first and second metal pads are in contact with each other to couple the first and second semiconductor chips to each other.

## Claims

### Claim 1

A semiconductor device comprising:
a chip stack structure comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip,
wherein the first semiconductor chip comprises:
a first substrate;
a first circuit layer on a front surface of the first substrate; and
a first connecting layer on the first circuit layer, the first connecting layer comprising a first metal pad electrically connected to the first circuit layer,
wherein the second semiconductor chip comprises:
a second substrate;
a second circuit layer on a front surface of the second substrate; and
a second connecting layer on the second circuit layer, the second connecting layer comprising a second metal pad electrically connected to the second circuit layer,
wherein the first connecting layer and the second connecting layer face each other,
wherein the first metal pad and the second metal pad are in contact with each other to couple the first and second semiconductor chips to each other,
wherein the first metal pad comprises a plurality of first metal pad portions separated from each other by first partitions,
wherein the second metal pad comprises a plurality of second metal pad portions separated from each other by second partitions, and
wherein at least one of the first and second semiconductor chips further comprises a through-via penetrating the respective substrate thereof.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein each of the first and second metal pads has a rectangular shape when viewed in a plan view, and
wherein the first and second metal pads intersect each other.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein at least one of the plurality of first metal pad portions is in contact with at least one of the plurality of second metal pad portions in a region of the first and second metal pads in which the first and second metal pads intersect.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the plurality of first metal pad portions are arranged in a long-axis direction of the first metal pad,
wherein each of the first partitions is between respective ones of the plurality of first metal pad portions that are adjacent each other,
wherein the plurality of second metal pad portions are arranged in a long-axis direction of the second metal pad, and
wherein each of the second partitions is between respective ones of the plurality of second metal pad portions that are adjacent each other.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the first metal pad has a first length in the long-axis direction of the first metal pad and a first width in a short-axis direction of the first metal pad, and
wherein a ratio of the first length to the first width is 2 or greater.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the second metal pad has a second length in the long-axis direction of the second metal pad and a second width in a short-axis direction of the second metal pad, and
wherein a ratio of the second length to the second width is 2 or greater.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first connecting layer further comprises:
a first upper insulating layer surrounding the first metal pad; and
a first bonding insulating layer on the first upper insulating layer and exposing the first metal pad,
wherein the second connecting layer further comprises:
a second upper insulating layer surrounding the second metal pad; and
a second bonding insulating layer on the second upper insulating layer and exposing the second metal pad, and
wherein the first bonding insulating layer is in contact with the second bonding insulating layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein at least one of the first partitions contacts the first upper insulating layer, and
wherein at least one of the second partitions contacts the second upper insulating layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the first partitions include a same material as the first upper insulating layer, and
wherein the second partitions include a same material as the second upper insulating layer.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor chip comprises a first through-via and the second semiconductor chip comprises a second through-via,
wherein the first through-via of the first semiconductor chip is electrically connected to the first metal pad, and
wherein the second through-via of the second semiconductor chip is electrically connected to the second metal pad.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the first semiconductor chip is a logic chip,
wherein the second semiconductor chip is a pixel array chip, and
wherein the second semiconductor chip further comprises:
at least one photoelectric conversion part in the second substrate; and
a micro lens on a back surface of the second substrate,
wherein the back surface of the second substrate is opposite to the front surface of the second substrate.

### Claim 12

A semiconductor device comprising:
a first chip stack structure comprising a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip,
wherein the first semiconductor chip comprises:
a first substrate;
a first circuit layer on a front surface of the first substrate; and
a first connecting layer on the first circuit layer, the first connecting layer comprising a first metal pad electrically connected to the first circuit layer,
wherein the second semiconductor chip comprises:
a second substrate;
a second circuit layer on a front surface of the second substrate; and
a second connecting layer on the second circuit layer, the second connecting layer comprising a second metal pad electrically connected to the second circuit layer,
wherein the first connecting layer and the second connecting layer face each other,
wherein the first metal pad and the second metal pad are in contact with each other to couple the first and second semiconductor chips to each other,
wherein the first metal pad comprises a plurality of first metal pad portions separated from each other by first partitions,
wherein the second metal pad comprises a plurality of second metal pad portions separated from each other by second partitions,
wherein the semiconductor device further comprises a second chip stack structure,
wherein the first chip stack structure and the second chip stack structure are vertically stacked and are vertically spaced apart from each other, and
wherein the first chip stack structure and the second chip stack structure are electrically connected to each other through connection terminals interposed therebetween.

### Claim 13

A semiconductor device comprising:
a first semiconductor chip comprising a first substrate, a first circuit layer on a front surface of the first substrate, and a first connecting layer on the first circuit layer; and
a second semiconductor chip comprising a second substrate, a second circuit layer on a front surface of the second substrate, and a second connecting layer on the second circuit layer,
wherein the first connecting layer comprises a first metal pad electrically connected to the first circuit layer,
wherein the first metal pad has a rectangular planar shape,
wherein the first metal pad comprises: a plurality of first metal pad portions arranged in a long-axis direction of the first metal pad; and first partitions between respective ones of the plurality of first metal pad portions,
wherein the second connecting layer comprises a second metal pad electrically connected to the second circuit layer,
wherein the second metal pad has a rectangular planar shape,
wherein the second metal pad comprises: a plurality of second metal pad portions arranged in a long-axis direction of the second metal pad; and second partitions between respective ones of the plurality of second metal pad portions,
wherein the second semiconductor chip is disposed on the first semiconductor chip in such a way that the first and second connecting layers are in contact with each other and the first and second metal pads intersect each other, and
wherein at least one of the first and second semiconductor chips further comprises a through-via penetrating the respective substrate thereof.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first circuit layer comprises:
a first integrated circuit;
first interlayer insulating layers covering the first integrated circuit; and
first metal lines in the first interlayer insulating layers,
wherein the second circuit layer comprises:
a second integrated circuit;
second interlayer insulating layers covering the second integrated circuit; and
second metal lines disposed in the second interlayer insulating layers, and
wherein the first and second connecting layers are between the first interlayer insulating layers and the second interlayer insulating layers.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first connecting layer further comprises: a first upper insulating layer on the first interlayer insulating layers; and a first bonding insulating layer covering a surface of the first upper insulating layer and exposing the first metal pad,
wherein the second connecting layer further comprises: a second upper insulating layer on the second interlayer insulating layers; and a second bonding insulating layer covering a surface of the second upper insulating layer and exposing the second metal pad, and
wherein the first bonding insulating layer is in contact with the second bonding insulating layer.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first metal pad penetrates the first upper insulating layer so as to be connected directly to at least one of the first metal lines, and
wherein the second metal pad penetrates the second upper insulating layer so as to be connected directly to at least one of the second metal lines.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, wherein the second semiconductor chip comprises the through-via,
wherein the through-via penetrates the second substrate so as to be electrically connected to the second metal pad, and
wherein the second semiconductor chip further comprises a bonding pad on a back surface of the second substrate so as to be electrically connected to the through-via.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising:
a package substrate on which the first and second semiconductor chips are disposed,
wherein the package substrate is electrically connected to the first and second semiconductor chips through the bonding pad.