# US 10,483,242 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,242 B2 - Document ID: US10483242B2 - Status: Granted - Kind: B2 - Application number: 16/077,270 - Filed: 2016-02-10 - Published: 2019-01-31 - Granted: 2019-11-19 - Earliest claimed: 2016-02-10 - Assignees: Ultramemory Inc. - Applicants: UltraMemory Inc. - Inventors: Naoki Ogawa; Toshitugu Ueda; Kazuo Yamaguchi - Web page: https://patentgrep.com/patent/US10483242B2 ## CPC - H10W 90/00: Package configurations - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - H04B 5/26: using coils - H04B 5/43: Antennas - H04B 5/48: Transceivers - H10B 12/00: Dynamic random access memory [DRAM] devices - H10D 1/20: Inductors - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/00: Interconnections or connectors in packages - H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G11C: STATIC STORES (semiconductor memory devices H10B) - H04B: TRANSMISSION - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device of the present invention is provided with a plurality of memory chips laminated to each other, each of said memory chips having: a first transmission/reception coil for communication by means of inductive coupling; first lead-out lines led out from both ends of the first transmission/reception coil; and a first transmission/reception circuit, which is connected to the first lead-out lines, and which inputs/outputs signals to/from the first transmission/reception coil. The semiconductor device is also provided with an interposer, which is disposed on one end in the laminating direction of the memory chips, and which has, for each of the memory chips: a second transmission/reception coil coupled to the first transmission/reception coil by means of inductive coupling; second lead-out lines led out from both ends of the second transmission/reception coil; and a second transmission/reception circuit, which is connected to the second lead-out lines, and which inputs/outputs signals to/from the second transmission/reception coil. The memory chips are disposed at positions where, in plan view, the first transmission/reception circuits overlap each other, and the first transmission/reception coils are disposed around the first transmission/reception circuits, said first transmission/reception coils being disposed at positions where the first transmission/reception coils do not overlap each other. ## Claims ### Claim 1 A semiconductor device comprising: a plurality of memory chips, that are laminated, each of which includes a first transmission/reception coil for communication using inductive coupling, a first lead-out line led out from both ends of the first transmission/reception coil, and a first transmission/reception circuit connected to the first lead-out line, being input and output signals between the first transmission/reception circuit and the first transmission/reception coil; and an interposer that is provided at one end in a direction in which the plurality of memory chips are laminated and includes, for each of the plurality of memory chips, a second transmission/reception coil which are coupled to the first transmission/reception coil by inductive coupling, a second lead-out line led out from both ends of each of the second transmission/reception coil, and a second transmission/reception circuit connected to the second lead-out line for inputting and outputting signals to and from the second transmission/reception coil, wherein the plurality of memory chips have a structure in which a plurality of the first transmission/reception circuits are disposed at positions that overlap each other in a plan view and the first transmission/reception coils are disposed in the vicinity of the first transmission/reception circuits at positions that do not overlap each other in a plan view. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first transmission/reception coils are symmetrically disposed in the vicinity of the first transmission/reception circuits in a plan view. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the first lead-out lines in the plurality of memory chips have the same length. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein central axes of the second transmission/reception coils are aligned with central axes of the corresponding first transmission/reception coils. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the second lead-out lines disposed in the interposer for each of the plurality of memory chips have the same length. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the interposer is a memory chip that is located at one end in the lamination direction among the plurality of memory chips which are laminated. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of memory chips are divided into a plurality of group units, and in the memory chips forming each group unit, the first transmission/reception coils are disposed at positions that overlap each other in a plan view, the first lead-out lines are disposed at positions that overlap each other in a plan view, and the first transmission/reception circuits are disposed at positions that overlap each other in a plan view. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the memory chips include arithmetic circuits that output different identification numbers in each other and comparison circuits that compare the identification numbers with a memory chip selection address and detect whether the identification numbers are matched with the memory chip selection address, and a signal line for the address is common to all of the memory chips. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the interposer generates the address and outputs the address.