# US 10,483,239 B2 · Semiconductor device including dual pad wire bond interconnection

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,239 B2
- Document ID: US10483239B2
- Status: Granted
- Kind: B2
- Application number: 15/907,600
- Filed: 2018-02-28
- Published: 2018-07-05
- Granted: 2019-11-19
- Earliest claimed: 2016-12-20
- Assignees: Sandisk Semiconductor (Shanghai) Co., Ltd.
- Applicants: Sandisk Semiconductor (Shanghai) Co., Ltd.
- Inventors: Junrong Yan; Xiaofeng Di; Harjashan Singh; Gokul Kumar; Chee Keong Chin; Ming Xia Wu; Jian Bin Gu
- Web page: https://patentgrep.com/patent/US10483239B2

## CPC

- H10W 90/00: Package configurations
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10P 58/00: Singulating wafers or substrates into multiple chips, i.e. dicing
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/0198: {batch processes}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/07511: {Treating the bonding area before connecting, e.g. by applying flux or cleaning}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5434: {the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5453: {connecting between multiple bond pads on a chip, e.g. daisy chain}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is disclosed including semiconductor die formed with a row of functional die bond pads and an adjacent row of dummy die bond pads. The functional die bond pads may be electrically connected to the integrated circuits formed within the semiconductor die. The dummy die bond pads may be formed in the scribe area of a semiconductor wafer from which the semiconductor die are formed, and are provided for wire bonding the semiconductor die within the semiconductor device.

## Claims

### Claim 1

A semiconductor die, comprising:
a first major surface;
a second major surface opposed to the first major surface;
integrated circuits formed adjacent the first major surface in an active area;
a set of functional die bond pads spaced inward from an edge of the semiconductor die and electrically connected to the integrated circuits by metal interconnects within the active area;
a set of dummy die bond pads at the edge of the semiconductor die and adjacent the set of functional die bond pads, the set of dummy die bond pads configured to receive a first set of bond wires; and
a second set of bond wires electrically interconnecting respective pairs of functional die bond pads from the set of functional die bond pads and dummy die bond pads from the set of dummy die bond pads.

### Claim 2 (depends on 1)

The semiconductor die of claim 1, wherein the set of dummy die bond pads have a severed edge.

### Claim 3 (depends on 1)

The semiconductor die of claim 1, further comprising at least one passivation layer in a space between the set of functional die bond pads and the set of dummy die bond pads.

### Claim 4 (depends on 1)

The semiconductor die of claim 1, wherein the set of functional die bond pads are positioned over the integrated circuits formed beneath a surface of the semiconductor die.

### Claim 5 (depends on 1)

The semiconductor die of claim 1, further comprising a seal ring formed beneath a surface of the semiconductor die, the set of functional die bond pads spaced inward from the edge of the semiconductor die a greater amount than an amount by which the seal ring is spaced inward from the edge of the semiconductor die.

### Claim 6 (depends on 5)

The semiconductor die of claim 5, further comprising one or more passivation layers formed on a surface of the semiconductor die over the seal ring.

### Claim 7 (depends on 1)

The semiconductor die of claim 1, wherein the integrated circuits are integrated circuits for flash memory.

### Claim 8

A semiconductor device, comprising:
a substrate;
a plurality of stacked semiconductor die mounted to the substrate, a semiconductor die of the stacked semiconductor die comprising:
integrated circuits formed adjacent the first major surface,
a set of first die bond pads spaced inward from an edge of the semiconductor die and electrically connected to the integrated circuits by metal interconnects, and
a set of second die bond pads at the edge of the semiconductor die and adjacent the set of first die bond pads; and
a plurality of wire bonds having a first end electrically coupled to the set of second die bond pads.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the plurality of stacked semiconductor die are stacked in an offset configuration.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the plurality of stacked semiconductor die comprise a first semiconductor die at a top of the stack and a second semiconductor die below adjacent to the first semiconductor die, wherein the set of first die bond pads in the second semiconductor die are covered beneath the first semiconductor die in the stack.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, further comprising an electrical connector electrically connecting pairs of the set of first die bond pads and the set of second die bond pads.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the semiconductor die comprises a first semiconductor die, the semiconductor device further comprising a second semiconductor die of the stacked semiconductor die, the second semiconductor die comprising:
a second set of integrated circuits formed adjacent the first major surface,
a second set of first die bond pads spaced inward from an edge of the semiconductor die and electrically connected to the second set of integrated circuits by metal interconnects, and
a second set of second die bond pads at the edge of the semiconductor die and adjacent the second set of first die bond pads.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the plurality of wire bonds have a second end, opposite the first end, the second end electrically coupled to the second set of second die bond pads on the second semiconductor die.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein the plurality of wire bonds have a second end, opposite the first end, the second end electrically coupled to the second set of function die bond pads on the second semiconductor die.

### Claim 15

A semiconductor die, comprising:
a first major surface;
a second major surface opposed to the first major surface;
integrated circuits formed adjacent the first major surface in an active area;
a set of functional die bond pads spaced inward from an edge of the semiconductor die and electrically connected to the integrated circuits by metal interconnects within the active area;
a set of dummy die bond pads at the edge of the semiconductor die and adjacent the set of functional die bond pads, the set of dummy die bond pads configured to receive a bond wire; and
a seal ring formed beneath a surface of the semiconductor die, the set of functional die bond pads spaced inward from the edge of the semiconductor die a greater amount than an amount by which the seal ring is spaced inward from the edge of the semiconductor die.

### Claim 16 (depends on 15)

The semiconductor die of claim 15, further comprising one or more passivation layers formed on a surface of the semiconductor die over the seal ring.

### Claim 17 (depends on 15)

The semiconductor die of claim 15, wherein the set of dummy die bond pads have a severed edge.

### Claim 18 (depends on 15)

The semiconductor die of claim 15, wherein the integrated circuits are formed beneath a surface of the semiconductor die and the set of functional die bond pads are positioned over the integrated circuits.

### Claim 19 (depends on 15)

The semiconductor die of claim 15, further comprising electrical conductors electrically interconnecting respective pairs of functional die bond pads from the set of functional die bond pads and dummy die bond pads from the set of dummy die bond pads.

### Claim 20 (depends on 19)

The semiconductor die of claim 19, wherein the electrical conductors comprise redistribution layer traces.

### Claim 21 (depends on 19)

The semiconductor die of claim 19, wherein the electrical conductors comprise conductive traces printed onto a surface of the semiconductor die.

### Claim 22 (depends on 19)

The semiconductor die of claim 19, wherein the electrical conductors comprise bond wires.