# US 10,483,236 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,236 B2 - Document ID: US10483236B2 - Status: Granted - Kind: B2 - Application number: 15/693,370 - Filed: 2017-08-31 - Published: 2018-09-27 - Granted: 2019-11-19 - Earliest claimed: 2017-03-22 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Masaji Iwamoto - Web page: https://patentgrep.com/patent/US10483236B2 ## CPC - H10W 90/00: Package configurations - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} - G11C 29/48: Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths - H10W 70/65: Shapes or dispositions of interconnections - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - G11C 2029/0401: {in embedded memories} - G11C 2029/1206: {Location of test circuitry on chip or wafer} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/611: {for connecting multiple chips together} - H10W 70/635: {Through-vias} - H10W 70/685: comprising multiple insulating layers - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/865: {Die-attach connectors and bond wires} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/284: {characterised by structural arrangements for measuring or testing} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor device includes a substrate having first and second principal surfaces, and a semiconductor chip disposed on the first principal surface. The substrate includes a first conductor layer disposed on the first principal surface, a second conductor layer disposed on the second principal surface, at least one third conductive layer between the first conductive layer and the second conductive layer, a detection interconnection disposed in either the first conductive layer or the third conductive layer, and first and second pads disposed on the second conductive layer and connected to the detection interconnection. The detection interconnection is not part of signal interconnections that are used during operation of the semiconductor chip and is not electrically connected to any circuit of the semiconductor chip. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate including an insulating layer, a first conductive layer on a first surface of the insulating layer, a second conductive layer on a second surface of the insulating layer that is opposite to the first surface, a third conductive layer extending in a plane direction of the substrate along the first and second surfaces in the insulating layer, and a via extending in a thickness direction of the substrate in the insulating layer; and a semiconductor chip disposed on a first principal surface of the substrate above the first surface, wherein the substrate further includes: a planar detection interconnection provided as part of either the first conductive layer or the third conductive layer, wherein the planar detection interconnection is not part of signal interconnections that are used during operation of the semiconductor chip and is not electrically connected to any circuit of the semiconductor chip, and a width of the planar detection interconnection is smaller than a width of the signal interconnections; and first and second pads to be connected to part of a ball grid array (BGA) or a land grid array (LGA), the first and second pads provided as part of the second conductive layer and electrically connected to the planar detection interconnection through the via. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the planar detection interconnection includes a serpentine region where the planar detection interconnection in the serpentine region is folded back and forth in a zigzag manner. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the serpentine region is disposed at a location corresponding to a part of an outer periphery of the semiconductor chip. ### Claim 4 (depends on 2) The semiconductor device according to claim 2, wherein the second conductive layer further includes a plurality of third pads electrically connected to the semiconductor chip, and the serpentine region is disposed at a location corresponding to one of the third pads. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the serpentine region is disposed at a location corresponding to one of the third pads provided on an outer side of the semiconductor chip. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein the planar detection interconnection in the serpentine region includes a plurality of linear portions and the linear portions extend perpendicular to the outer side of the semiconductor chip. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the planar detection interconnection includes first and second serpentine regions where the planar detection interconnection in each of the first and second serpentine regions is folded back and forth in a zigzag manner. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the planar detection interconnection in the first serpentine region includes a plurality of first linear portions that extend in a first direction and the planar detection interconnection in the second serpentine region includes a plurality of second linear portions that extend in a second direction crossing the first direction. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the first and second directions are perpendicular to each other. ### Claim 10 A semiconductor package, comprising: a substrate including an insulating layer, a first conductive layer on a first surface of the insulating layer, a second conductive layer on a second surface of the insulating layer that is opposite to the first surface, a third conductive layer extending in a plane direction of the substrate along the first and second surfaces in the insulating layer, and a via extending in a thickness direction of the substrate in the insulating layer; a plurality of semiconductor chips stacked on a first principal surface of the substrate above the first surface; and a plurality of external terminals disposed on a second principal surface of the substrate opposite to the first principal surface, the plurality of external terminals being a ball grid array (BGA) or a land grid array (LGA), wherein the substrate further includes: signal interconnections provided as part of the first conductive layer and electrically connected to the semiconductor chips; a planar detection interconnection provided as part of either the first conductive layer or the third conductive layer, wherein the planar detection interconnection is not electrically connected to any of the signal interconnections, and a width of the planar detection interconnection is smaller than a width of the signal interconnections; and first and second pads connected to part of the external terminals, the first and second pads provided as part of the second conductive layer and electrically connected to the planar detection interconnection through the via. ### Claim 11 (depends on 10) The semiconductor package according to claim 10, wherein the planar detection interconnection includes a serpentine region where the planar detection interconnection in the serpentine region is folded back and forth in a zigzag manner. ### Claim 12 (depends on 11) The semiconductor package according to claim 11, wherein the serpentine region is disposed at a location corresponding to a part of an outer periphery of one of the semiconductor chips. ### Claim 13 (depends on 11) The semiconductor package according to claim 11, wherein the second conductive layer further includes a plurality of third pads electrically connected to the one of the semiconductor chips, and the serpentine region is disposed at a location corresponding to one of the third pads. ### Claim 14 (depends on 13) The semiconductor package according to claim 13, wherein the serpentine region is disposed at a location corresponding to one of the third pads provided on an outer side of the one of the semiconductor chips. ### Claim 15 (depends on 14) The semiconductor package according to claim 14, wherein the planar detection interconnection in the serpentine region includes a plurality of linear portions and the linear portions extend perpendicular to the outer side of the one of the semiconductor chips. ### Claim 16 (depends on 10) The semiconductor package according to claim 10, wherein the planar detection interconnection includes first and second serpentine regions where the planar detection interconnection in each of the first and second serpentine regions is folded back and forth in a zigzag manner. ### Claim 17 (depends on 10) The semiconductor package according to claim 10, wherein the planar detection interconnection in the first serpentine region includes a plurality of first linear portions that extend in a first direction and the planar detection interconnection in the second serpentine region includes a plurality of second linear portions that extend in a second direction crossing the first direction. ### Claim 18 (depends on 17) The semiconductor package according to claim 17, wherein the first and second directions are perpendicular to each other.