# US 10,483,235 B2 · Stacked electronic device and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,235 B2 - Document ID: US10483235B2 - Status: Granted - Kind: B2 - Application number: 15/057,973 - Filed: 2016-03-01 - Published: 2016-11-10 - Granted: 2019-11-19 - Earliest claimed: 2015-05-08 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Yu-Cheng Chiao; Tung-Yi Chan; Chen-Hsi Lin; Chia Hua Ho; Meng-Chang Chan; Hsin-Hung Chou - Web page: https://patentgrep.com/patent/US10483235B2 ## CPC - H10W 90/00: Package configurations - H10W 20/4473: {Conductive organic materials, e.g. conductive adhesives or conductive inks} - H10W 20/48: Insulating materials thereof - H10W 70/098: {Applying pastes or inks, e.g. screen printing (H10W70/095 takes precedence)} - H10W 70/635: {Through-vias} - H10W 74/131: {the semiconductor body being only partially enclosed} - H10P 14/46: using a liquid - H10W 20/071: {of dielectric parts thereof} - H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/66: Conductive materials thereof - H10W 72/072: {of bump connectors} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/922: {Bond pads being integral with underlying chip-level interconnections} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method for fabricating a stacked electronic device is provided. A first three-dimensional (3D) printing is performed to form a first insulating layer and a plurality of first redistribution layers (RDLs) on a first substrate. A second 3D printing is performed to form a second substrate and a plurality of through-substrate vias (TSVs) on the first insulating layer, in which the plurality of TSVs is electrically connected to the plurality of first RDLs. A third 3D printing is performed to form a second insulating layer and a plurality of second RDLs on the second substrate, in which the plurality of second RDLs is electrically connected to the plurality of TSVs. A plurality of contacts of a third substrate is bonded to the plurality of second RDLs, so that the substrate is mounted onto the second insulating layer. The disclosure also provides a stacked electronic device formed by such a method. ## Claims ### Claim 1 A method for fabricating a stacked electronic device, comprising: providing a first substrate, wherein the first substrate comprises a wafer, a chip, or a combination thereof; performing a first three-dimensional (3D) printing to form a first insulating layer and a plurality of first redistribution layers (RDLs) on the first substrate, wherein the plurality of first RDLs is embedded in the first insulating layer and is electrically connected to contacts of the first substrate; performing a second 3D printing to form a second substrate, a plurality of through-substrate vias (TSVs) and insulating spacers on the first insulating layer simultaneously and respectively by at least three print heads, wherein the plurality of TSVs pass through the second substrate and are electrically connected to the plurality of first RDLs, and the insulating spacers electrically isolate the second substrate from the plurality of TSVs; performing a third 3D printing to form a second insulating layer and a plurality of second RDLs on the second substrate, wherein the plurality of second RDLs is embedded in the second insulating layer and electrically connected to the plurality of TSVs; and bonding a plurality of contacts of a third substrate to the plurality of second RDLs, so that the third substrate is mounted onto the second insulating layer. ### Claim 2 (depends on 1) The method as claimed in claim 1, wherein the first insulating layer and the second insulating layer comprise a ceramic material, a polymer material, a resin material, or a dielectric material. ### Claim 3 (depends on 1) The method as claimed in claim 1, wherein the plurality of first RDLs and the plurality of second RDLs comprise aluminum, copper, gold, or their alloys. ### Claim 4 (depends on 1) The method as claimed in claim 1, wherein the second substrate comprises a molding compound material, a ceramic material, a polymer material, a resin material, or a dielectric material. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein the second substrate comprises a semiconductor material. ### Claim 6 (depends on 1) The method as claimed in claim 1, wherein the plurality of TSVs comprises tungsten, aluminum, copper, gold, lead-free solder, or their alloys. ### Claim 7 (depends on 1) The method as claimed in claim 1, wherein a 3D printer employed to perform the first and third 3D printings has at least two print heads, so that at least two different materials are simultaneously formed during each of the first and third 3D printings. ### Claim 8 (depends on 1) The method as claimed in claim 1, wherein the insulating spacers comprise a ceramic material, a polymer material, a resin material, or a dielectric material. ### Claim 9 (depends on 1) The method as claimed in claim 1, wherein the third substrate is a wafer, a chip, or a combination thereof. ### Claim 10 (depends on 1) The method as claimed in claim 1, wherein the second substrate is thicker than the first insulating layer and the second insulating layer. ### Claim 11 (depends on 1) The method as claimed in claim 1, wherein aspect ratios of the plurality of TSVs are higher than aspect ratios of the plurality of first RDLs and aspect ratios of the plurality of second RDLs. ### Claim 12 (depends on 1) The method as claimed in claim 1, wherein the plurality of first RDLs and the plurality of second RDLs comprise a multi-layer conductive structure.