# US 10,483,234 B2 · Chip packages and methods of manufacture thereof

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- Number: US 10,483,234 B2
- Document ID: US10483234B2
- Status: Granted
- Kind: B2
- Application number: 15/636,272
- Filed: 2017-06-28
- Published: 2017-10-19
- Granted: 2019-11-19
- Earliest claimed: 2015-09-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Wei Wu; Jing-Cheng Lin; Szu-Wei Lu; Ying-Ching Shih
- Web page: https://patentgrep.com/patent/US10483234B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 74/014: {using batch processing}
- H10W 74/016: {using moulds}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07354: {changes in dispositions}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9413: {on encapsulations}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/10: Configurations of laterally-adjacent chips
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip including a plurality of first contact pads, the plurality of first contact pads facing the RDL; a second chip disposed between the first chip and the redistribution layer (RDL) wherein a portion of the first chip is disposed outside a lateral extent of the second chip; and a conductive via laterally separated from the second chip, the conductive via extending between the RDL and a first contact pad of the plurality of first contact pads, the first contact pad located in the portion of the first chip disposed outside the lateral extent of the second chip.

## Claims

### Claim 1

A chip package comprising:
a plurality of first chips laterally adjacent to each other, each of the plurality of first chips having a plurality of first contact pads on a first surface thereof;
first redistribution layers (RDLs) at the first surfaces of the first chips, wherein the first RDLs are separate from each other, wherein each of the first RDLs contacts the first surface of a respective first chip and is laterally conterminous with the respective first chip;
a second chip attached to the first surfaces of the plurality of first chips, the second chip having a plurality of second contact pads on a first surface thereof, wherein the first surface of the second chip faces away from the plurality of first chips, wherein a first portion of the second chip is disposed within lateral extents of a third chip of the plurality of first chips, and a second portion of the second chip is disposed within lateral extents of a fourth chip of the plurality of first chips;
an adhesive layer between the second chip and the plurality of first chips, the adhesive layer being attached to and contacting a second surface of the second chip opposing the first surface of the second chip, the adhesive layer having a same width as the second chip, a first portion of the adhesive layer being attached to the third chip of the plurality of first chips, and a second portion of the adhesive layer being attached to the fourth chip of the plurality of first chips;
a second RDL coupled to the plurality of second contact pads of the second chip, wherein the second chip is between the second RDL and the plurality of first chips;
a plurality of first conductive pillars laterally separated from the second chip, the plurality of first conductive pillars extending from the second RDL to corresponding ones of a first group of the plurality of first contact pads, the first group disposed outside a width of the second chip; and
a molding compound around the plurality of first chips, the second chip, and the plurality of first conductive pillars.

### Claim 2 (depends on 1)

The chip package of claim 1, wherein the plurality of first chips comprises dynamic random access memory (DRAM) chips, and wherein the second chip comprises a logic chip.

### Claim 3 (depends on 1)

The chip package of claim 1, wherein the first RDLs are disposed between the plurality of first chips and the adhesive layer.

### Claim 4 (depends on 1)

The chip package of claim 1, further comprising a plurality of second conductive pillars between the second RDL and the plurality of second contact pads of the second chip, wherein the plurality of second conductive pillars are surrounded by a polymer layer.

### Claim 5 (depends on 4)

The chip package of claim 4, wherein the polymer layer has a different composition than that of the molding compound.

### Claim 6 (depends on 4)

The chip package of claim 4, wherein the polymer layer has a same width as the second chip.

### Claim 7 (depends on 1)

The chip package of claim 1, further comprising a heat sink attached to second surfaces of the plurality of first chips opposing the first surfaces of the plurality of first chips.

### Claim 8

A method for forming a semiconductor package, the method comprising:
attaching a first die and a second die to a carrier, the first die being laterally adjacent to the second die;
forming a first conductive pillar over a first contact pad of the first die, the first contact pad being on an upper surface of the first die facing away from the carrier;
forming a second conductive pillar over a second contact pad of the second die, the second contact pad being on an upper surface of the second die facing away from the carrier;
attaching a third die to the upper surface of the first die and to the upper surface of the second die, wherein the first die and the second die extend beyond lateral extents of the third die, wherein the third die has a third conductive pillar over a third contact pad of the third die, wherein the third contact pad is on an upper surface of the third die facing away from the carrier;
depositing, in a single process, a molding material around the first die, the second die, the third die, the first conductive pillar, and the second conductive pillar;
recessing the molding material, wherein after the recessing, an upper surface of the molding material is level with an upper surface of the first conductive pillar, an upper surface of the second conductive pillar, and an upper surface of the third conductive pillar; and
forming a first redistribution layer (RDL) over and electrically coupled to the first conductive pillar, the second conductive pillar, and the third conducive pillar.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming a second RDL over the first contact pad of the first die before forming the first conductive pillar.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a third RDL over the second contact pad of the second die before forming the second conductive pillar, wherein the second RDL is separated from the third RDL.

### Claim 11 (depends on 9)

The method of claim 9, wherein forming the second RDL comprises forming the second RDL over the first contact pad of the first die and over the second contact pad of the second die before forming the first conductive pillar and second conductive pillar.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
forming external connectors over an upper surface of the first RDL facing away from the carrier; and
removing the carrier after forming the external connectors.

### Claim 13

A method comprising:
attaching a first side of a first die to a carrier, wherein the first die has a first conductive pillar disposed over a first contact pad on a second side of the first die opposing the first side of the first die;
forming a first redistribution layer (RDL) between the first conductive pillar and the first contact pad of the first die, wherein sidewalls of the first RDL are aligned with respective sidewalls of the first die;
attaching a first side of a second die to the carrier such that the second die is laterally adjacent to the first die, wherein the second die has a second conductive pillar disposed over a second contact pad on a second side of the second die opposing the first side of the second die;
forming a second RDL between the second conductive pillar and the second contact pad of the second die, wherein sidewalls of the second RDL are aligned with respective sidewalls of the second die, wherein the first RDL and the second RDL are spaced apart from each other;
attaching a third die to the second side of the first die and to the second side of the second die, wherein a first portion of the third die extends outside a lateral extent of the first die, and a second portion of the third die extends outside a lateral extent of the second die;
after the first die, the second die and the third die are attached, embedding the first die, the second die, the third die, the first conductive pillar and the second conductive pillar in a molding layer, wherein the molding layer extends continuously from the first side of the first die to a first side of the third die facing away from the first die;
thinning the molding layer, wherein after the thinning, the molding layer, the first conductive pillar, the second conductive pillar, and a third conductive pillar of the third die have a coplanar upper surface; and
forming a third RDL over the molding layer, wherein the third RDL is electrically coupled to the first conductive pillar, the second conductive pillar and the third conductive pillar.

### Claim 14 (depends on 13)

The method of claim 13, wherein after attaching the third die, the third die is between the first conductive pillar and the second conductive pillar.

### Claim 15 (depends on 13)

The method of claim 13, wherein attaching the third die comprises attaching the third die to the first die and to the second die using an adhesive layer, wherein the adhesive layer contacts the second side of the third die, and extends continuously from the first die to the second die.

### Claim 16 (depends on 13)

The method of claim 13, wherein the molding layer extends to a location between a first sidewall of the first RDL and a second sidewall of the second RDL facing the first sidewall.

### Claim 17 (depends on 13)

The method of claim 13, wherein the embedding comprises forming the molding layer in a single process step to embed the first die, the second die, the third die, the first conductive pillar and the second conductive pillar in the molding layer.

### Claim 18 (depends on 1)

The chip package of claim 1, wherein a first one of the first RDLs has a first sidewall that faces a second sidewall of a second one of the first RDLs, wherein the molding compound contacts the first sidewall and the second sidewall.

### Claim 19 (depends on 1)

The chip package of claim 1, wherein the adhesive layer extends continuously from the first portion of the adhesive layer to the second portion of the adhesive layer.

### Claim 20 (depends on 10)

The method of claim 10, wherein sidewalls of the first RDL are formed to be aligned with sidewalls of the first die, and sidewalls of the second RDL are formed to be aligned with sidewalls of the second die.