# US 10,483,233 B2 · Split ball grid array pad for multi-chip modules

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- Number: US 10,483,233 B2
- Document ID: US10483233B2
- Status: Granted
- Kind: B2
- Application number: 15/416,447
- Filed: 2017-01-26
- Published: 2017-05-18
- Granted: 2019-11-19
- Earliest claimed: 2015-09-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Anson J. Call; Erwin B. Cohen; Dany Minier; Wolfgang Sauter; David B. Stone; Eric W. Tremble
- Web page: https://patentgrep.com/patent/US10483233B2

## CPC

- H10W 90/00: Package configurations
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/90: Bond pads, in general
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/655: Fan-out layouts
- H10W 70/685: comprising multiple insulating layers
- H10W 72/019: {of bond pads}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/931: {Shapes of bond pads}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.

## Claims

### Claim 1

A multi-chip module, comprising:
a substrate containing multiple wiring layers, each wiring layer having multiple wires, first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, wherein the first section is connected by a first wire of the multiple wires to a pad of a first group of the first pads, wherein the non-contiguous second section is connected by a second wire of the multiple wires to a pad of a second group of the first pads, and wherein another pad of the second pads is a conventional pad having a contiguous top surface and a contiguous bottom surface;
a first solder ball in direct physical contact with the contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height in a first direction, and wherein the first direction is perpendicular to the contiguous bottom surface of the conventional pad; and
a second solder ball in direct physical contact with the first section and the non-contiguous second section of the split pad, wherein the second solder ball has a second height in the first direction, and wherein the second height is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging,
wherein a first active component is attached to the first group of the first pads and a second active component is attached to the second group of the first pads.

### Claim 2 (depends on 1)

The multi-chip module of claim 1, wherein the split-pad, including the gap, occupies an area of the bottom surface of the substrate equal to the area of the bottom surface of the substrate occupied by the conventional pad having the contiguous top surface.

### Claim 3 (depends on 1)

The multi-chip module of claim 1, wherein an area of a top surface of the first section is greater than an area of a top surface of the non-contiguous second section.

### Claim 4 (depends on 1)

The multi-chip module of claim 1,
wherein the first section has the shape of a first circular segment bounded by a first arc of a circle and by a first chord connecting the endpoints of the first arc,
wherein the non-contiguous second section has the shape of a second circular segment bounded by a second arc of the circle and by a second chord connecting the endpoints of the second arc,
wherein the gap defined the space between the first and second cord, and
wherein a first radius of the first circular segment is the same as a second radius of the second circular segment, the first and second radius measured from the center of the circle.

### Claim 5 (depends on 1)

The multi-chip module of claim 1, further comprising:
a first set of wires of the multiple wiring layers directly connecting a first set of the first group of the first pads to a first set of the second group of the first pads;
a second set of wires of the multiple wiring layers connecting a second set of the first group of the first pads to a first set of the second pads; and
a third set of wires of the multiple wiring layers connecting a second set of the second group of the first pads to a second set of the second pads.

### Claim 6 (depends on 1)

The multi-chip module of claim 1, wherein the first active component is a first integrated circuit chip and the second active component is a second integrated circuit chip.

### Claim 7 (depends on 1)

The multi-chip module of claim 1, wherein the first active component includes first component pads attached to the first group of the first pads by solder bumps and the second active component includes second component pads attached to the second group of the first pads by solder bumps.

### Claim 8

A method of fabricating a multi-chip module, said method comprising:
providing a substrate containing multiple wiring layers, each wiring layer having multiple wires, first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, wherein the first section is connected by a first wire of the multiple wires to a pad of a first group of the first pads, wherein the non-contiguous second section is connected by a second wire of the multiple wires to a pad of a second group of the first pads, and wherein another pad of the second pads is a conventional pad having a contiguous top surface and a contiguous bottom surface;
placing a first solder ball in direct physical contact with the contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height in a first direction, and wherein the first direction is perpendicular to the contiguous bottom surface of the conventional pad;
placing a second solder ball in direct physical contact with the first section and the non-contiguous second section of the split pad, wherein the second solder ball has a second height in the first direction, and wherein the second height is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging,
attaching a first active component to the first group of the first pads; and
attaching a second active component to the second group of the first pads.

### Claim 9 (depends on 8)

The method of claim 8, wherein the split-pad, including the gap, occupies an area of the bottom surface of the substrate equal to the area of the bottom surface of the substrate occupied by the conventional pad having the contiguous top surface.

### Claim 10 (depends on 8)

The method of claim 8, wherein an area of a top surface of the first section is greater than an area of a top surface of the non-contiguous second section.

### Claim 11 (depends on 8)

The method of claim 8,
wherein the first section has the shape of a first circular segment bounded by a first arc of a circle and by a first chord connecting the endpoints of the first arc,
wherein the non-contiguous second section has the shape of a second circular segment bounded by a second arc of the circle and by a second chord connecting the endpoints of the second arc,
wherein the gap defined the space between the first and second cord, and
wherein a first radius of the first circular segment is the same as a second radius of the second circular segment, the first and second radius measured from the center of the circle.

### Claim 12 (depends on 8)

The method of claim 8, said method further comprising:
wherein a first set of wires of the multiple wiring layers directly connect a first set of the first group of the first pads to a first set of the second group of the first pads,
wherein a second set of wires of the multiple wiring layers connect a second set of the first group of the first pads to a first set of the second pads, and
wherein a third set of wires of the multiple wiring layers connect a second set of the second group of the first pads to a second set of the second pads.

### Claim 13 (depends on 8)

The method of claim 8, said method further comprising:
after said attaching the first active component and before said attaching the second active component, performing a first test to test the first active component using the first section of the split pad and passing the first test.

### Claim 14 (depends on 8)

The method of claim 8, said method further comprising:
after said attaching the second active component, electrically connecting the first section of the split pad to the second non-contiguous section of the split pad; and
after said electrically connecting the first section of the split pad to the non-contiguous second section of the split pad, performing a second test to test the multi-chip module.

### Claim 15 (depends on 14)

The method of claim 14, wherein said electrically connecting the first section of the split pad to the non-contiguous second section of the split pad comprises forming the second solder ball extending over the first section of the split pad and the second non-contiguous section of the split pad.

### Claim 16 (depends on 8)

The method of claim 8, wherein the first active component is a first integrated circuit chip and the second active component is a second integrated circuit chip.

### Claim 17 (depends on 8)

The method of claim 8, wherein the first active component includes first component pads attached to the first group of the first pads by solder bump, and wherein the second active component includes second component pads attached to the second group of the first pads by solder bumps.