# US 10,483,226 B2 · Semiconductor device and method of forming the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,226 B2 - Document ID: US10483226B2 - Status: Granted - Kind: B2 - Application number: 15/957,919 - Filed: 2018-04-20 - Published: 2019-10-24 - Granted: 2019-11-19 - Earliest claimed: 2018-04-20 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Chin-Yu Ku; Hon-Lin Huang; Chao-Yi Wang; Chen-Shien Chen; Chien-Hung Kuo - Web page: https://patentgrep.com/patent/US10483226B2 ## CPC - H10W 72/0198: {batch processes} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/012: {of bump connectors, dummy bumps or thermal bumps} - H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates} - H10W 72/01208: {using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks} - H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01255: {by using masks} - H10W 72/01953: {by etching} - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/234: {Cross-sectional shape, i.e. in side view} - H10W 72/242: {relative to the surface, e.g. recessed, protruding} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/283: {Reinforcing structures, e.g. bump collars} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method of forming a semiconductor device is provided. A first substrate is provided with a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump. A first insulating layer is formed over the metal bump and the passivation stack. First and second patterning processes are performed to form first and second opening patterns in the first insulating layer. The metal bump is exposed by the second patterning process. A second substrate is provided with a second insulating layer thereon. The second substrate is bonded to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer. The first insulating layer and a portion of the passivation stack are removed. ## Claims ### Claim 1 A method of forming a semiconductor device, comprising: providing a first substrate having a conductive feature therein, a first metal bump over the conductive feature and a passivation stack aside the first metal bump; forming a first insulating layer over the first metal bump and the passivation stack; performing a first patterning process to form a first opening pattern in the first insulating layer; performing a second patterning process to form a second opening pattern in the first insulating layer, wherein the first metal bump is exposed by the second patterning process; providing a second substrate having a second insulating layer thereon; bonding the second substrate to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer; and removing the first insulating layer and a portion of the passivation stack. ### Claim 2 (depends on 1) The method of claim 1, wherein a dimension of the first opening pattern is different from a dimension of the second opening pattern. ### Claim 3 (depends on 2) The method of claim 2, wherein the dimension comprises a depth, a width, a length or a combination thereof. ### Claim 4 (depends on 1) The method of claim 1, wherein a shape of the first opening pattern is different from a shape of the second opening pattern. ### Claim 5 (depends on 1) The method of claim 1, wherein a shape of the first opening pattern is the same as a shape of the second opening pattern. ### Claim 6 (depends on 1) The method of claim 1, wherein the first substrate further has a second metal bump aside the passivation stack, and the second metal bump is not exposed by the second patterning process. ### Claim 7 (depends on 1) The method of claim 1, wherein the second patterning process is performed after the first patterning process. ### Claim 8 (depends on 1) The method of claim 1, wherein the first metal bump has a protruding part, and the protruding part of the first metal bump is embedded in the passivation stack and separated from the conductive feature. ### Claim 9 A method of forming a semiconductor device, comprising: providing a first substrate having at least two chip regions separated by an insulating deep trench, wherein the first substrate has, in each chip region, a conductive feature therein, a metal bump over the conductive feature and a passivation stack aside the metal bump; forming a first insulating layer over the metal bumps and the passivation stacks; patterning the first insulating layer to form a first opening pattern and a second opening pattern therein, wherein a bottom of the first opening pattern and a bottom of the second opening pattern are at different height levels; providing a second substrate having a second insulating layer thereon; bonding the second substrate to the first substrate with the second insulating layer and the first insulating layer facing each other, so that the second insulating layer fills in the first and second opening patterns of the first insulating layer; and removing the first insulating layer and portions of the passivation stacks by flowing an etch gas from the insulating deep trench. ### Claim 10 (depends on 9) The method of claim 9, further comprising debonding the second substrate from the first substrate, so as to separate the chip regions from each other. ### Claim 11 (depends on 9) The method of claim 9, wherein the metal bump is exposed by one of the first opening pattern and the second opening pattern. ### Claim 12 (depends on 9) The method of claim 9, wherein the first opening pattern has a shape of a circle, a rectangle, a bar, a polygon or a combination thereof. ### Claim 13 (depends on 9) The method of claim 9, wherein the first opening pattern corresponds to the insulating deep trench or at least one of the passivation stacks. ### Claim 14 (depends on 9) The method of claim 9, wherein the metal bump has, in each chip region, a curved bottom that extends under a portion of the passivation stack.