# US 10,483,225 B2 · Packaging assembly and method of making the same

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- Number: US 10,483,225 B2
- Document ID: US10483225B2
- Status: Granted
- Kind: B2
- Application number: 15/904,812
- Filed: 2018-02-26
- Published: 2018-06-28
- Granted: 2019-11-19
- Earliest claimed: 2011-07-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chita Chuang; Yao-Chun Chunag; Tsung-Shu Lin; Chen-Cheng Kuo; Chen-Shien Chen
- Web page: https://patentgrep.com/patent/US10483225B2

## CPC

- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/019: {of bond pads}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01238: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01255: {by using masks}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A packaging assembly includes a semiconductor device. The semiconductor device includes a conductive pad having a first width, and an under-bump metallization (UBM) layer on the conductive pad, wherein the UBM layer has a second width greater than the first width. The semiconductor device further includes a conductive pillar on the UBM layer, and a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer. The packaging assembly further includes a substrate. The substrate includes a conductive region, and a mask layer overlying the substrate and exposing a portion of the conductive region. The packaging assembly further includes a joint solder structure between the conductive pillar and the conductive region.

## Claims

### Claim 1

A packaging assembly, comprising:
a semiconductor device comprising:
a conductive pad having a first width,
a passivation layer over the conductive pad, wherein the passivation layer directly contacts the conductive pad,
a protective layer over the passivation layer, wherein the protective layer directly contacts the conductive pad,
an under-bump metallization (UBM) layer directly contacting the conductive pad, wherein the UBM layer has a second width greater than the first width,
a conductive pillar on the UBM layer, and
a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the UBM layer;
a substrate comprising:
a conductive region, and
a mask layer overlying the substrate and exposing a portion of the conductive region; and
a joint solder structure between the conductive pillar and the conductive region.

### Claim 2 (depends on 1)

The packaging assembly of claim 1, wherein the mask layer has a mask opening exposing a portion of the conductive region, and the width of the mask opening is smaller than and the second width.

### Claim 3 (depends on 2)

The packaging assembly of claim 2, wherein a ratio between the width of the mask opening and the second width ranges from about 0.7 and about 0.8.

### Claim 4 (depends on 1)

The packaging assembly of claim 1, wherein the conductive pillar comprises a copper pillar, and the conductive region is a copper trace.

### Claim 5 (depends on 1)

The packaging assembly of claim 1, wherein the mask layer is a solder resist layer.

### Claim 6

A packaging assembly, comprising:
a semiconductor device, wherein the semiconductor device comprises:
a conductive pad having a first width,
a conductive pillar over the conductive pad, wherein the conductive pillar has a second width greater than the first width, and
a cap layer over the conductive pillar, wherein the cap layer exposes sidewalls of the conductive pillar layer;
a substrate, wherein the substrate comprises:
a conductive region, and
a mask layer over the conductive region, wherein the mask layer defines an opening exposing a portion of the conductive region; and
a joint structure electrically connecting the conductive pillar and the conductive region wherein the joint structure extends through the opening.

### Claim 7 (depends on 6)

The packaging assembly of claim 6, wherein the semiconductor device further comprises an under bump metallization (UBM) layer between the conductive pillar and the conductive pad.

### Claim 8 (depends on 7)

The packaging assembly of claim 7, wherein the UBM layer has the second width.

### Claim 9 (depends on 7)

The packaging assembly of claim 7, wherein the semiconductor device further comprises a protective layer over the conductive pad, and the protective layer defines an opening exposing a portion of the conductive pad.

### Claim 10 (depends on 9)

The packaging assembly of claim 9, wherein the UBM layer directly contacts the exposed portion of the conductive pad.

### Claim 11 (depends on 9)

The packaging assembly of claim 9, wherein the opening has a third width less than the first width.

### Claim 12 (depends on 6)

The packaging assembly of claim 6, wherein the opening has a fourth width less than the second width.

### Claim 13 (depends on 6)

The packaging assembly of claim 6, wherein the semiconductor device further comprises a second conductive pillar, wherein a ratio between the second width and a pitch between the conductive pillar and the second conductive pillar ranges from about 0.65 to about 0.8.

### Claim 14 (depends on 6)

The packaging assembly of claim 6, wherein the semiconductor device further comprises a second conductive pillar, wherein a ratio between the first width and a pitch between the conductive pillar and the second conductive pillar ranges from about 0.5 to about 0.6.

### Claim 15

A method of making a packaging assembly, the method comprising:
depositing an under bump metallization (UBM) layer over a conductive pad of a semiconductor device, wherein the conductive pad has a first width;
depositing a mask layer over the UBM layer;
patterning the mask layer to define an opening having a second width greater than the first width;
forming a conductive pillar in the opening;
depositing a cap layer over the conductive pillar in the opening;
removing the mask layer; and
bonding the conductive pillar to a conductive region of a substrate using a joint structure, wherein the cap layer is between the conductive pillar and the joint structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein the bonding of the conductive pillar to the conductive region comprises reflowing the joint structure.

### Claim 17 (depends on 15)

The method of claim 15, further comprising forming a solder layer over the cap layer in the opening, wherein the bonding of the conductive pillar to the conductive region comprises reflowing the solder layer.

### Claim 18 (depends on 15)

The method of claim 15, further comprising etching the UBM layer to have the second width, wherein the etching of the UBM layer comprises using the conductive pillar as a mask.

### Claim 19 (depends on 1)

The packaging assembly of claim 1, wherein the protective layer extends along a sidewall of the passivation layer.

### Claim 20 (depends on 1)

The packaging assembly of claim 1, wherein the passivation layer exposes a first portion of the conductive pad, the protective layer exposes a second portion of the conductive pad, and a ratio of a width of the second portion to a width of the first portion ranges from 0.7 to 0.9.