# US 10,483,222 B1 · Semiconductor device and manufacturing method thereof

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- Number: US 10,483,222 B1
- Document ID: US10483222B1
- Status: Granted
- Kind: B1
- Application number: 15/383,923
- Filed: 2016-12-19
- Granted: 2019-11-19
- Earliest claimed: 2010-03-19
- Assignees: Amkor Technology, Inc.
- Applicants: Amkor Technology, Inc.
- Inventors: Jong Sik Paek; Eun Sook Sohn; In Bae Park; Won Chul Do; Glenn A. Rinne
- Web page: https://patentgrep.com/patent/US10483222B1

## CPC

- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/652: Cross-sectional shapes
- H10W 70/654: Top-view layouts
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/01257: {by reflowing}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/232: {Plan-view shape, i.e. in top view}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/283: {Reinforcing structures, e.g. bump collars}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device and a manufacturing method thereof are disclosed. A first insulation layer is formed on a semiconductor die, a redistribution layer electrically connected to a bond pad is formed on the first insulation layer, and a second insulation layer covers the redistribution layer. The second insulation layer is made of a cheap, non-photosensitive material. Accordingly, the manufacturing cost of the semiconductor device can be reduced.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor die comprising:
a top die surface; and
a bond pad on the top die surface;
a conductive layer comprising a first end coupled to the bond pad, wherein the conductive layer extends laterally from the bond pad over the top die surface;
a conductive interconnection structure coupled to a second end of the conductive layer; and
an insulation layer formed directly on the conductive interconnection structure and on the conductive layer, the insulation layer comprising a single continuous layer of a non-photosensitive material that laterally surrounds a lower portion of the conductive interconnection structure and does not laterally surround an upper portion of the conductive interconnection structure,
wherein:
the lower portion of the conductive interconnection structure that is surrounded by the insulation layer is shaped like a portion of a sphere, the portion of the sphere comprising a curvature in a vertical cross-sectional view; and
the single continuous layer of the non-photosensitive material that laterally surrounds the lower portion of the conductive interconnection structure conforms, in the vertical cross-sectional view, to said curvature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the insulation layer comprises a bottom side that faces toward the semiconductor die, and a top side that is exposed from the completed semiconductor device.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein:
the conductive layer comprises only a seed layer and a single electroplated layer on the seed layer; and
the conductive interconnection structure is entirely above the conductive layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the single continuous layer of the non-photosensitive material is formed to laterally surround and conform to a pre-existing shape of the conductive interconnection structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the insulation layer is directly on the conductive layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein:
a first contacting surface of the single continuous layer of the non-photosensitive material directly contacts the conductive interconnection structure; and
no part of the first contacting surface is linear.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, comprising a passivation layer between the insulation layer and the top die surface, wherein the passivation layer comprises an aperture through which the bond pad is coupled to the first end of the conductive layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, comprising a lower insulation layer between the conductive layer and the passivation layer, the lower insulation layer comprising a photosensitive material and a bond pad aperture through which the bond pad is coupled to the first end of the conductive layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein no portion of any lateral side surface of the conductive interconnection structure is straight.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein:
the conductive layer comprises a pad with a diameter D and a trace extending from the pad with a width of W;
the conductive interconnection structure is coupled to the pad and has a height greater than 235 um; and
W is less than half of D.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the first end of the conductive layer is directly coupled to the bond pad.

### Claim 12

A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor die that comprises:
a top die surface; and
a bond pad on the top die surface;
providing a conductive layer comprising a first end coupled to the bond pad, wherein the conductive layer extends laterally from the bond pad over the top die surface;
providing a conductive interconnection structure coupled to a second end of the conductive layer; and
providing an insulation layer formed directly on the conductive interconnection structure and on the conductive layer, the insulation layer comprising a single continuous layer of a non-photosensitive material that laterally surrounds a lower portion of the conductive interconnection structure and does not laterally surround an upper portion of the conductive interconnection structure,
wherein:
the lower portion of the conductive interconnection structure that is surrounded by the insulation layer is shaped like a portion of a sphere, the portion of the sphere comprising a curvature in a vertical cross-sectional view; and
the single continuous layer of the non-photosensitive material that laterally surrounds the lower portion of the conductive interconnection structure conforms, in the vertical cross-sectional view, to said curvature.

### Claim 13 (depends on 12)

The method of claim 12, wherein the insulation layer comprises a bottom side that faces toward the semiconductor die, and a top side that is exposed from the completed semiconductor device.

### Claim 14 (depends on 12)

The method of claim 12, wherein:
the conductive layer comprises only a seed layer and a single electroplated layer on the seed layer; and
the conductive interconnection structure is entirely above the conductive layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the lower portion of the conductive interconnection structure that is surrounded by the insulation layer comprises a convex conductive surface portion that is convex in a direction toward the provided conductive layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the conductive interconnection structure comprises an upper convex conductive surface portion that is convex in a direction away from the conductive layer and protrudes upward from the insulation layer.

### Claim 17 (depends on 12)

The method of claim 12, wherein the single continuous layer of the non-photosensitive material is formed to laterally surround and conform to a pre-existing shape of the conductive interconnection structure.

### Claim 18 (depends on 12)

The method of claim 12, wherein the insulation layer is directly on the conductive layer.

### Claim 19 (depends on 12)

The method of claim 12, wherein:
a first contacting surface of the single continuous layer of the non-photosensitive material directly contacts the conductive interconnection structure; and
no part of the first contacting surface is linear.