# US 10,483,221 B2 · 3DI solder cup

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- Number: US 10,483,221 B2
- Document ID: US10483221B2
- Status: Granted
- Kind: B2
- Application number: 15/797,638
- Filed: 2017-10-30
- Published: 2019-05-02
- Granted: 2019-11-19
- Earliest claimed: 2017-10-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Kyle K. Kirby
- Web page: https://patentgrep.com/patent/US10483221B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/01221: {using local deposition}
- H10W 72/01231: {using blanket deposition}
- H10W 72/01251: {Changing the shapes of bumps}
- H10W 72/01255: {by using masks}
- H10W 72/01931: {using blanket deposition}
- H10W 72/01951: {Changing the shapes of bond pads}
- H10W 72/01955: {by using masks}
- H10W 72/072: {of bump connectors}
- H10W 72/07202: {using auxiliary members}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07354: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/234: {Cross-sectional shape, i.e. in side view}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/245: {of outermost layers of multilayered bumps, e.g. bump coating being only on a part of a bump core}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/255: {of outermost layers of multilayered bumps, e.g. material of a coating}
- H10W 72/283: {Reinforcing structures, e.g. bump collars}
- H10W 72/287: {Flow barriers}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 72/987: {Flow barriers}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate or semiconductor device, semiconductor device assembly, and method of forming a semiconductor device assembly that includes a barrier on a solder cup. The semiconductor device assembly includes a substrate disposed over another substrate. At least one solder cup extends from one substrate towards an under bump metal (UBM) on the other substrate. The barrier on the exterior of the solder cup may be a standoff to control a bond line between the substrates. The barrier may reduce solder bridging during the formation of a semiconductor device assembly. The barrier may help to align the solder cup with a UBM when forming a semiconductor device assembly and may reduce misalignment due to lateral movement of substrates and/or semiconductor devices.

## Claims

### Claim 1

A semiconductor device assembly comprising:
a first substrate having a first surface and a second surface opposite the first surface, the first surface having at least one under bump metal (UBM) disposed thereon;
a second substrate having a first surface and a second surface opposite the first surface, the second substrate disposed over the first substrate, the second substrate having at least one solder cup on the second surface, the at least one solder cup comprising a pillar and a barrier on an exterior of the pillar, the barrier having a first end proximal to the second surface of the second substrate and a second end distal to the second surface of the second substrate, the barrier extends from the first end to the second end along the exterior of the pillar and being open at the second end, the pillar comprising solder positioned within an interior of the barrier, the opening at the second end of the barrier having a first perimeter and the UBM having a second perimeter, the first perimeter being larger than the second perimeter;
wherein the solder cup and UBM are connected together to form a support between the first substrate and the second substrate; and
wherein the UBM is encased by the solder positioned within the interior of the barrier.

### Claim 2 (depends on 1)

The assembly of claim 1, wherein the solder cup and UBM form an interconnect that electrically connects the first substrate and the second substrate.

### Claim 3 (depends on 2)

The assembly of claim 2, wherein the first substrate further comprises a first semiconductor device and the second substrate further comprises a second semiconductor device.

### Claim 4 (depends on 3)

The assembly of claim 3, wherein the second end of the barrier engages the first surface of the first semiconductor device and supports the second semiconductor device.

### Claim 5 (depends on 1)

The assembly of claim 1, wherein the second end of the barrier surrounds the UBM.

### Claim 6 (depends on 1)

The assembly of claim 1, wherein the barrier is configured to prevent the solder from bridging with an adjacent feature on the first surface of the first substrate.

### Claim 7 (depends on 1)

The assembly of claim 1, wherein the barrier is tapered having a smaller diameter at the first end than a diameter at the second end.

### Claim 8 (depends on 1)

The assembly of claim 1, wherein the barrier has a smaller perimeter at the first end than a perimeter at the second end.

### Claim 9 (depends on 1)

The assembly of claim 1, the UBM having a first end proximal to the first side of the first substrate, a second end distal to the first side of the first substrate, and sidewalls extending from the first end to the second end.

### Claim 10 (depends on 9)

The assembly of claim 9, wherein the sidewalls of the UBM are tapered having a smaller diameter at the first end than a diameter at the second end.

### Claim 11 (depends on 9)

The assembly of claim 9, wherein the UBM has a smaller perimeter at the first end than a perimeter at the second end.

### Claim 12 (depends on 1)

The assembly of claim 1, wherein the barrier comprises at least one of tantalum, tungsten, titanium nitride, or combinations thereof.

### Claim 13 (depends on 1)

The assembly of claim 1, wherein the UBM comprises nickel or gold.

### Claim 14 (depends on 13)

The assembly of claim 13, wherein the UBM does not comprise copper.

### Claim 15 (depends on 1)

The assembly of claim 1, wherein the UBM includes sidewalls and the sidewalls are completely encased by the solder positioned within the interior of the barrier.

### Claim 16

A semiconductor device comprising:
a substrate having a first surface and a second surface opposite the first surface;
at least one under bump metal (UBM) extending from the second surface of the substrate;
at least one solder cup connected to the first surface of the substrate, the at least one solder cup having an external barrier with sidewalls that form an interior, the sidewalls of the external barrier having a proximal end and a distal end positioned away from the first surface, the sidewalls of the external barrier being open at the distal end, wherein the external barrier is electrically conductive; and
metal positioned entirely within the interior formed by the sidewalls of the external barrier, wherein the external barrier comprises at least one of tantalum, tungsten, titanium nitride, or combinations thereof.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein the at least one solder cup is electrically connected to the at least one UBM.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, further comprising a plurality of layers positioned between the first surface of the substrate and the solder cup.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the at least one solder cup is electrically connected to the at least one UBM by a via in the substrate and electrical interconnects within the plurality of layers positioned between the first surface of the substrate and the solder cup.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the metal comprises solder.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, wherein the metal further comprises nickel and copper.

### Claim 22 (depends on 21)

The semiconductor device of claim 21, wherein the nickel extends between the sidewalls of the external barrier and the nickel separates the solder from the copper.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, wherein the solder is positioned adjacent to the distal end of the sidewalls of the external barrier.

### Claim 24 (depends on 23)

The semiconductor device of claim 23, wherein the copper is positioned adjacent to the proximal end of the sidewalls of the external barrier.