# US 10,483,220 B2 · Method of manufacturing semiconductor devices and corresponding device

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- Number: US 10,483,220 B2
- Document ID: US10483220B2
- Status: Granted
- Kind: B2
- Application number: 15/239,545
- Filed: 2016-08-17
- Published: 2017-08-03
- Granted: 2019-11-19
- Earliest claimed: 2016-02-01
- Assignees: Stimicroelectronics S.R.L.
- Applicants: Stmicroelectronics S.R.L.
- Inventors: Andrea Paleari; Antonella Milani; Lucrezia Guarino; Federica Ronchi
- Web page: https://patentgrep.com/patent/US10483220B2

## CPC

- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/039: {also covering sidewalls of the conductive structures}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 72/00: Interconnections or connectors in packages
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/652: Cross-sectional shapes
- H10W 70/66: Conductive materials thereof
- H10W 70/69: Insulating materials thereof
- H10W 72/019: {of bond pads}
- H10W 72/01908: {using permanent auxiliary members, e.g. using alignment marks}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01953: {by etching}
- H10W 72/01955: {by using masks}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In one embodiment, a method manufactures a semiconductor device including metallizations having peripheral portions with one or more underlying layers having marginal regions extending facing the peripheral portions. The method includes: providing a sacrificial layer to cover the marginal regions of the underlying layer, providing the metallizations while the marginal regions of the underlying layer are covered by the sacrificial layer, and removing the sacrificial layer so that the marginal regions of the underlying layer extend facing the peripheral portions in the absence of contact interface therebetween, thereby avoiding thermo-mechanical stresses.

## Claims

### Claim 1

A semiconductor device, comprising:
a first layer having a via and a marginal region;
metallizations partially extending in the via in the first layer and having peripheral portions facing the marginal region of said first layer without contacting the marginal region and separated from the marginal region by an undercut gap, at least a portion of the metallizations being lower than an upper surface of the first layer; and
a first barrier layer extending in the via and having a peripheral portion extending on the marginal region of the first layer, the peripheral portion of the first barrier layer being separated from the peripheral portions of the metallizations by the undercut gap.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein said metallizations include:
a metallization body, and
an outer surface coating on said body, wherein said marginal region faces said peripheral portions without a contact interface with both said metallization body and said outer surface coating.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising a second barrier layer underlying said metallization body and adjoining said outer surface coating, the second barrier layer and outer surface coating together surround said metallization body.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein said first layer includes a passivation layer and the first barrier layer extends on the passivation layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein said first barrier layer extends under said metallization body.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein said first barrier layer extends on said passivation layer only at said marginal region.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein:
said passivation layer includes a dielectric passivation layer, and/or
said first barrier layer includes titanium tungsten.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein said metallizations include Cu-RDL metallizations.

### Claim 9

A semiconductor device, comprising:
a dielectric layer;
a passivation layer on the dielectric layer, the passivation layer having a marginal region;
a first metallization layer extending in a via through the passivation layer, at least a portion of the first metallization layer being positioned lower than an upper surface of the passivation layer;
a second metallization layer coating a top surface of the first metallization layer and having a peripheral portion coating a side surface of the first metallization layer, the peripheral portion having an end that faces the marginal region of the passivation layer and separated from the marginal region by an undercut gap that extends inward beyond the end; and
a first barrier layer extending in the via and on the marginal region of the passivation layer, the first barrier layer being positioned below the first metallization layer and being separated from the end of the peripheral portion of the second metallization by the undercut gap.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a barrier layer underlying the first metallization layer and adjoining the second metallization layer, the barrier layer and second metallization layer together encapsulating the first metallization layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, further comprising a third metallization layer coating outside surfaces of the second metallization layer, the third metallization layer having a peripheral portion coating the peripheral portion of the second metallization layer and having an end that faces the marginal region of the passivation layer without contacting the marginal region.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein:
the passivation layer extends lengthwise in a first direction;
the peripheral portion of the second metallization layer extends lengthwise in a second direction perpendicular to the first direction and has an end face; and
the end face of the peripheral portion of the second metallization layer faces the marginal region of the passivation layer and is spaced apart from the marginal region by a gap.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, further comprising:
a second barrier layer underlying said first metallization layer and contacting the second metallization layer, the second barrier layer and second metallization layer together encapsulating the first metallization layer.

### Claim 14

A semiconductor device, comprising:
a passivation layer having a marginal region;
a first metallization layer extending in a via through the passivation layer, at least a portion of the first metallization layer being positioned in the via lower than an upper surface of the passivation layer;
a first conductive barrier layer extending in the via, underlying said first metallization layer, and extending on the marginal region of the passivation layer; and
a second conductive barrier layer extending in the via and over the marginal region of the passivation layer between the first metallization and the first conductive barrier layer, the first conductive barrier layer having a first portion positioned in the via and contacting a bottom surface of the first metallization layer and a second portion positioned on the marginal region of the passivation layer and spaced apart from the second barrier layer by an undercut gap.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising a second metallization layer coating a top surface of the first metallization layer and having a peripheral portion coating a side surface of the first metallization layer, the peripheral portion having an end that faces the marginal region of the passivation layer without contacting the marginal region.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the second conductive barrier layer contacts the second metallization layer, the second conductive barrier layer and second metallization layer together encapsulating the first metallization layer.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, further comprising a third metallization layer coating outside surfaces of the second metallization layer, the third metallization layer having a peripheral portion coating the peripheral portion of the second metallization layer and having an end that faces the marginal region of the passivation layer without contacting the marginal region.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein:
the passivation layer extends lengthwise in a first direction;
the peripheral portion of the second metallization layer extends lengthwise in a second direction perpendicular to the first direction and has an end face; and
the end face of the peripheral portion of the second metallization layer faces the marginal region of the passivation layer and is spaced apart from the marginal region by the gap.

### Claim 19 (depends on 14)

The semiconductor device of claim 14, further comprising a third conductive barrier layer having a first portion positioned between and contacting the first and second conductive barrier layers in the via and a second portion positioned between the first and second conductive barrier layers above the marginal region of the passivation layer, the second portion of the third conductive barrier layer being spaced apart from the first conductive barrier layer.