# US 10,483,219 B2 · Array substrate with static charge releasing pattern and method for producing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,219 B2 - Document ID: US10483219B2 - Status: Granted - Kind: B2 - Application number: 15/502,132 - Filed: 2016-08-12 - Published: 2018-02-15 - Granted: 2019-11-19 - Earliest claimed: 2016-01-04 - Assignees: Boe Technology Group Co., Ltd.; Chengdu Boe Optoelectronics Technology Co., Ltd. - Applicants: Boe Technology Group Co., Ltd.; Chengdu BOE Optoelectronics Technology Co., Ltd. - Inventors: Xiaofei Yang; Zailong Mo; Yanxia Xin; Ke Dai; Yawen Zhu; Lei Su - Web page: https://patentgrep.com/patent/US10483219B2 ## CPC - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures} - H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/443: {adapted for preventing breakage, peeling or short circuiting} - H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs} - H10D 86/60: wherein the TFTs are in active matrices - H10D 89/911: {using passive elements as protective elements} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An array substrate includes a metal pattern and an electrically conductive pattern formed sequentially on a base substrate. The electrically conductive pattern is insulated from the metal pattern; and a static charge releasing pattern is formed in a same layer as the electrically conductive pattern and formed by a same material as the electrically conductive pattern, the static charge releasing pattern being insulated from the electrically conductive pattern and electrically connected with the metal pattern. ## Claims ### Claim 1 An array substrate, comprising a metal pattern and an electrically conductive pattern formed sequentially on a base substrate, the electrically conductive pattern being insulated from the metal pattern, wherein the array substrate further comprises: a static charge releasing pattern formed in a same layer as the electrically conductive pattern and formed by a same material as the electrically conductive pattern, wherein the static charge releasing pattern is insulated from the electrically conductive pattern and electrically connected with the metal pattern, and wherein the metal pattern is a signal line, the signal line being continuous and comprising an input end and an output end, and the static charge releasing pattern comprises: a first static charge releasing pattern portion arranged in a crimping region of the array substrate and connected with the input end of the signal line; and a second static charge releasing pattern portion arranged in a display region of the array substrate and connected with the output end of the signal line. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein an insulation layer is provided between the electrically conductive pattern and the metal pattern; and wherein a via hole is provided in the insulation layer and at least one of the first static charge releasing pattern portion or the second static charge releasing pattern portion is electrically connected to the metal pattern through the via hole. ### Claim 3 (depends on 1) The array substrate according to claim 1, wherein the first static charge releasing pattern portion is in the shape of a rectangle having an area of 25 μm2 to 400 μm2. ### Claim 4 (depends on 2) The array substrate according to claim 2, wherein the first static charge releasing pattern portion is in the shape of a rectangle having an area of 25 μm2 to 400 μm2. ### Claim 5 (depends on 1) The array substrate according to claim 1, wherein the first static charge releasing pattern portion is electrically connected with the signal line through at least two via holes in the insulation layer. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein the metal pattern is a gate line and the electrically conductive pattern comprises a pattern of a source-drain metal layer. ### Claim 7 (depends on 6) The array substrate according to claim 6, wherein the electrically conductive pattern further comprises a data line. ### Claim 8 (depends on 1) The array substrate according to claim 1, wherein the metal pattern is a gate line and the electrically conductive pattern comprises a transparent electrode and a pattern of a source-drain metal layer, and the static charge releasing pattern comprises: a first portion formed in a same layer as the pattern of the source-drain metal layer and formed by a same material as the pattern of the source-drain metal layer; a second portion formed in a same layer as the transparent electrode and formed by a same material as the transparent electrode. ### Claim 9 (depends on 8) The array substrate according to claim 8, wherein the transparent electrode is a common electrode or a pixel electrode. ### Claim 10 (depends on 1) The array substrate according to claim 1, wherein the metal pattern is a data line and the electrically conductive pattern comprises a transparent electrode. ### Claim 11 (depends on 10) The array substrate according to claim 10, wherein the transparent electrode is a common electrode or a pixel electrode. ### Claim 12 A method for manufacturing an array substrate, comprising a step of forming a metal pattern and an electrically conductive pattern on a base substrate sequentially, wherein in a patterning process of forming the electrically conductive pattern, a static charge releasing pattern insulated from the electrically conductive pattern and electrically connected to the metal pattern is also formed, the static charge releasing pattern being formed in a same layer as the electrically conductive pattern and formed by the same material as the electrically conductive pattern, wherein the metal pattern is a signal line, the signal line being continuous and comprising an input end and an output end, and the static charge releasing pattern comprises: a first static charge releasing pattern portion arranged in a crimping region of the array substrate and connected with the input end of the signal line; and a second static charge releasing pattern portion arranged in a display region of the array substrate and connected with the output end of the signal line. ### Claim 13 (depends on 12) The method according to claim 12, further comprising a step of: forming an insulation layer which is arranged between the electrically conductive pattern and the metal pattern and has a via hole, wherein at least one of the first static charge releasing pattern portion or the second static charge releasing pattern portion is electrically connected to the metal pattern through the via hole. ### Claim 14 A method of manufacturing an array substrate, comprising: forming a gate line and a gate insulation layer sequentially; forming one or more first via holes in the gate insulation layer; forming a source-drain metal pattern and a first portion of a static charge releasing pattern in a same layer and of a same material by means of a single patterning process, the first portion of the static charge releasing pattern being electrically connected to the gate line through the first via hole formed in the gate insulation layer; depositing a passivation layer; forming one or more second via holes in the passivation layer; and forming a transparent electrode and a second portion of the static charge releasing pattern in a same layer and of a same material by means of a single patterning process, the second portion of the static charge releasing pattern being electrically connected to the first portion of the static charge releasing pattern through the second via hole formed in the passivation layer, wherein the gate line is continuous and comprises an input end and an output end, wherein the static charge releasing pattern comprises: a first static charge releasing pattern portion arranged in a crimping region of the array substrate and connected with the input end of the gate line; and a second static charge releasing pattern portion arranged in a display region of the array substrate and connected with the output end of the gate line.