# US 10,483,218 B2 · Integrated circuit (IC) devices with varying diameter via layer

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- Number: US 10,483,218 B2
- Document ID: US10483218B2
- Status: Granted
- Kind: B2
- Application number: 16/428,441
- Filed: 2019-05-31
- Published: 2019-09-19
- Granted: 2019-11-19
- Earliest claimed: 2016-11-29
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: William Michael Stone
- Web page: https://patentgrep.com/patent/US10483218B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 90/00: Package configurations
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit (IC) device that includes an IC device layer, at least one electrical connection layer located over the IC device layer, and a varying diameter via layer located over the at least one electrical connection layer. The varying diameter via layer includes (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias. The plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region. The varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

## Claims

### Claim 1

An integrated circuit (IC) device comprising:
an IC device layer; and
at least one electrical connection layer located over the IC device layer; and
a varying diameter via layer located over the at least one electrical connection layer, the varying diameter via layer comprising (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias,
wherein the plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region, and
wherein the varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

### Claim 2 (depends on 1)

The IC device of claim 1, wherein the varying diameter via layer is part of a redistribution layer of the IC device.

### Claim 3 (depends on 1)

The IC device of claim 1, further comprising a passivation layer laterally surrounding the plurality of interior region vias and the plurality of perimeter region vias, wherein the varying diameter via layer is part of the passivation layer via.

### Claim 4 (depends on 1)

The IC device of claim 1, further comprising a first plurality of bumps coupled to the plurality of interior region vias.

### Claim 5 (depends on 4)

The IC device of claim 4, further comprising a second plurality of bumps coupled to the plurality of perimeter region vias.

### Claim 6 (depends on 5)

The IC device of claim 5, wherein the first plurality of bumps is larger than the second plurality of bumps.

### Claim 7 (depends on 1)

The IC device of claim 1, wherein a size of at least one of the interior region vias is configured to reduce a risk of tensile stress damage to the IC device.

### Claim 8 (depends on 1)

The IC device of claim 1, wherein a size of at least one of the perimeter region vias is configured to reduce a risk of sheer stress damage to the IC device.

### Claim 9 (depends on 1)

The IC device of claim 1, wherein at least one interior region via has a size or shape configured based on an amount of tensile stress.

### Claim 10 (depends on 1)

The IC device of claim 1, wherein at least one perimeter region via has a size or shape configured based on an amount of sheer stress.

### Claim 11 (depends on 1)

The IC device of claim 1, wherein each of the plurality of interior region vias has a width and the widths of the plurality of interior region vias increase toward a center of the varying diameter via layer.

### Claim 12 (depends on 11)

The IC device of claim 11, wherein the widths of the plurality of interior region vias increases step-wise toward the center of the varying diameter via layer.

### Claim 13 (depends on 1)

The IC device of claim 1, wherein the IC device is incorporated into a device selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

### Claim 14

A method for fabricating an integrated circuit (IC) device, comprising:
providing an IC device layer;
forming at least one electrical connection layer over the IC device layer; and
forming a varying diameter via layer over the at least one electrical connection layer, the varying diameter via layer comprising (i) an interior region having a plurality of interior region vias and (ii) a perimeter region having a plurality of perimeter region vias,
wherein the plurality of interior region vias of the interior region is larger than the plurality of perimeter region vias of the perimeter region, and
wherein the varying diameter via layer comprises an interior surface that is coupled to an interior surface of the at least one electrical connection layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the varying diameter via layer is part of a redistribution layer of the IC device.

### Claim 16 (depends on 14)

The method of claim 14, further comprising forming a passivation layer that laterally surrounds the plurality of interior region vias and the plurality of perimeter region vias, wherein the varying diameter via layer is part of the passivation layer via.

### Claim 17 (depends on 14)

The method of claim 14, further comprising coupling a first plurality of bumps to the plurality of interior region vias.

### Claim 18 (depends on 17)

The method of claim 17, further comprising coupling a second plurality of bumps to the plurality of perimeter region vias.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first plurality of bumps is larger than the second plurality of bumps.

### Claim 20 (depends on 18)

The method of claim 18, wherein each of the plurality of interior region vias has a width and the widths of the plurality of interior region vias increase toward a center of the varying diameter via layer.