# US 10,483,216 B2 · Power module and fabrication method for the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,216 B2 - Document ID: US10483216B2 - Status: Granted - Kind: B2 - Application number: 15/372,123 - Filed: 2016-12-07 - Published: 2017-03-30 - Granted: 2019-11-19 - Earliest claimed: 2014-06-13 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Katsuhiko Yoshihara - Web page: https://patentgrep.com/patent/US10483216B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10D 12/441: {Vertical IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 62/8325: {Silicon carbide} - H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates} - H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps} - H10W 70/047: {Attaching leadframes to insulating supports, e.g. for tape automated bonding [TAB]} - H10W 70/417: {Bonding materials between chips and die pads} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 70/435: {of insulating layers on leadframes, e.g. bridging members} - H10W 70/456: {Materials} - H10W 70/457: {of metallic layers on leadframes} - H10W 70/465: {Bumps or wires} - H10W 70/466: {Tape carriers or flat leads} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices - H10W 90/00: Package configurations - H10W 90/811: {Multiple chips on leadframes} - H10D 64/111: {Field plates} - H10W 72/07336: {Soldering or alloying} - H10W 72/07554: {changes in dispositions} - H10W 72/07636: {Soldering or alloying} - H10W 72/07652: {changes in structures or sizes} - H10W 72/07653: {changes in shapes} - H10W 72/5363: {the connected ends being wedge-shaped} - H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements} - H10W 72/547: {Dispositions of multiple bond wires} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/627: {Multiple strap connectors having different structures or shapes} - H10W 72/646: {the connected ends being on auxiliary connecting means on bond pads, e.g. on a bump connector} - H10W 72/652: {comprising metals or metalloids, e.g. silver} - H10W 72/871: {Bond wires and strap connectors} - H10W 72/884: {Die-attach connectors and bond wires} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 76/12: characterised by their shape - H10W 76/47: Solid or gel fillings - H10W 76/60: Seals - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/764: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The power module includes: a ceramics substrate; a source electrode pattern, a drain electrode pattern, a source signal electrode pattern, and a gate signal electrode pattern respectively disposed on the ceramics substrate; a semiconductor device disposed on the drain electrode pattern, the semiconductor device comprising a source pad electrode and a gate pad electrode at a front surface side; a divided leadframe for source bonded to the source electrode pattern and the source pad electrode; and a divided leadframe for gate pad electrode bonded to a gate pad electrode. There is provided a power module having a simplified structure, fabricated through a simplified process, and capable of conducting a large current; and a fabrication method for such a power module. ## Claims ### Claim 1 A power module comprising: a substrate; a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate; a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed; and a leadframe bonded to an upper surface of the semiconductor device, wherein the leadframe is divided into a plurality of leadframes, wherein the leadframe divided into the plurality of frames comprises: a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and a second leadframe electrically insulated from the first leadframe, the power module further comprising: a first bonding wire connecting between the first leadframe and the first signal electrode pattern; and a second bonding wire connecting between the second leadframe and the second signal electrode pattern. ### Claim 2 (depends on 1) The power module according to claim 1, wherein assembling connection between the first leadframe and the second leadframe is performed via an insulating portion. ### Claim 3 (depends on 2) The power module according to claim 2, wherein the insulating portion comprises an epoxy based resin or a silicone based resin. ### Claim 4 (depends on 1) The power module according to claim 1, wherein the substrate comprises an insulating substrate. ### Claim 5 (depends on 4) The power module according to claim 4, wherein the insulating substrate comprises any one selected from the group consisting of a direct bonding copper substrate, a direct brazed aluminum substrate and an active metal bond substrate. ### Claim 6 (depends on 1) The power module according to claim 1, wherein the semiconductor device comprises a first pad electrode and a second pad electrode at a front surface side, wherein the first leadframe is bonded to the first electrode pattern and the first pad electrode, and the second leadframe is bonded to the second pad electrode. ### Claim 7 (depends on 1) The power module according to claim 1, wherein the first leadframe comprises any one selected from the group consisting of Cu, Al, a Cu alloy, an Al alloy, and an alloy containing at least one of the metals, and the second leadframe comprises any one selected from the group consisting of Cu, Al, and CuMo. ### Claim 8 (depends on 1) The power module according to claim 1, wherein the substrate comprises an organic insulating resin layer. ### Claim 9 (depends on 1) The power module according to claim 1, wherein the power module comprises any one selected from the group consist of 1-in-1 module, 2-in-1 module, 4-in-1 module, 6-in-1 module, and 7-in-1 module. ### Claim 10 (depends on 1) The power module according to claim 1, wherein the semiconductor device comprises any one selected from the group consist of IGBT, a diode, Si based MISFET, SiC based MISFET, and GaNFET. ### Claim 11 (depends on 1) The power module according to claim 1, wherein the first electrode pattern and the second electrode pattern are directly disposed on the substrate. ### Claim 12 A power module comprising: a substrate; a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate; a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed; and a leadframe bonded to an upper surface of the semiconductor device, wherein the leadframe is divided into a plurality of leadframes, wherein the leadframe divided into the plurality of frames comprises: a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and a second leadframe electrically insulated from the first leadframe, the power module further comprising: a third leadframe electrically connected to the first leadframe, the third leadframe being disposed on the first signal electrode pattern; and a fourth leadframe electrically connected to the second leadframe, the fourth leadframe being disposed on the second signal electrode pattern. ### Claim 13 (depends on 12) The power module according to claim 12, wherein a material of the third leadframe and a material of the first leadframe are the same. ### Claim 14 (depends on 12) The power module according to claim 12, wherein a material of the fourth leadframe and a material of the second leadframe are the same. ### Claim 15 A power module comprising: a substrate; a first electrode pattern, a second electrode pattern, a first signal electrode pattern, and a second signal electrode pattern respectively disposed on the substrate; a semiconductor device disposed on a first surface of the second electrode pattern, the first surface being opposite to a second surface of the second electrode pattern on which the substrate is disposed; a leadframe bonded to an upper surface of the semiconductor device; a first soldering layer disposed on the first pad electrode; a stress relaxation layer disposed on the first soldering layer, the stress relaxation layer configured to relax a stress applied to the first soldering layer; and a second soldering layer disposed on the stress relaxation layer, wherein the leadframe is divided into a plurality of leadframes, wherein the leadframe divided into the plurality of frames comprises: a first leadframe configured to conduct a principal current, the first leadframe being bonded to the first electrode pattern and the upper surface of the semiconductor device, and a second leadframe electrically insulated from the first leadframe, wherein the semiconductor comprises a first pad electrode and a second pad electrode at a front surface side, wherein the first leadframe is bonded to the first electrode pattern and the first pad electrode, the second leadframe is bonded to the second pad electrode, and the first leadframe is connected to the first pad electrode via the stress relaxation layer. ### Claim 16 (depends on 15) The power module according to claim 15, wherein the stress relaxation layer is formed by including a metal layer having low coefficient of thermal expansion (CTE). ### Claim 17 (depends on 16) The power module according to claim 16, wherein the metal layer having low CTE comprises any one selected from the group consisting of CuMo, CuW, Mo, and W. ### Claim 18 (depends on 16) The power module according to claim 16, wherein the stress relaxation layer comprises any one selected from the group consisting of Cu, Al, covar, and invar.