# US 10,483,215 B2 · Wafer level integration including design/co-design, structure process, equipment stress management and thermal management

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,215 B2
- Document ID: US10483215B2
- Status: Granted
- Kind: B2
- Application number: 15/272,838
- Filed: 2016-09-22
- Published: 2018-03-22
- Granted: 2019-11-19
- Earliest claimed: 2016-09-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jeffrey Gelorme; Li-Wen Hung; John U. Knickerbocker
- Web page: https://patentgrep.com/patent/US10483215B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 90/00: Package configurations
- H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/016: {of strap connectors}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07231: {Techniques}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07235: {Applying EM radiation, e.g. induction heating or using a laser}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07338: {hardening the adhesive by curing, e.g. thermosetting}
- H10W 72/225: {Bumps having a filler embedded in a matrix}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/295: {optical coupling}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A multi-layer wafer and method of manufacturing such wafer are provided. The method includes applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

## Claims

### Claim 1

A multi-layer wafer comprising:
two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer, the polymer layer having a polymer composition of a molecular weight polymethylmethacrylate polymer at a level of 10-50% with added liquid multifunctional acrylates forming the remaining 50-90% of the polymer composition, the two heterogeneous wafers low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.

### Claim 2 (depends on 1)

The multi-layer wafer of claim 1, wherein the stress compensating polymer layer comprises at least one of a thermal plastic, an adhesive composition or co-polymer having adhesion.

### Claim 3 (depends on 1)

The multi-layer wafer of claim 1, further comprising islands of heterogeneous material in at least one heterogeneous wafer.

### Claim 4 (depends on 3)

The multi-layer wafer of claim 3, further comprising:
channels between the islands of heterogeneous material; and
one of an oxide or a polymer channel deposition to fill the channels.

### Claim 5 (depends on 4)

The multi-layer wafer of claim 4, wherein the channels are back filled with one of oxide or polymer to create a channel oxide deposition.

### Claim 6 (depends on 1)

The multi-layer wafer of claim 1, wherein each of the two heterogeneous wafers are formed from at least one of: complementary metal-oxide semiconductor (CMOS) and GaN on Si, CMOS and glass, CMOS and sapphire, CMOS and SiC on Si, CMOS and diamond on Si, or CMOS and sapphire on Si.

### Claim 7 (depends on 1)

The multi-layer wafer of claim 1, wherein the stress compensating polymer layer has a thickness determined by a viscosity of a liquid polymer applied to the at least one of the two heterogeneous wafers and a spin speed.

### Claim 8 (depends on 1)

The multi-layer wafer of claim 1, wherein the stress compensating polymer layer comprises a free-standing sheet of dry polymer film bonded to the least one heterogeneous wafer.

### Claim 9 (depends on 1)

The multi-layer wafer of claim 1, further comprising a promoter added to at least one of the heterogeneous wafers or the stress compensating polymer layer.

### Claim 10 (depends on 1)

The multi-layer wafer of claim 1, the stress compensating polymer layer is UV cured.

### Claim 11 (depends on 1)

The multi-layer wafer of claim 1, wherein at least one of the heterogeneous wafers of the multi-layer wafer pair is thinned.

### Claim 12 (depends on 1)

The multi-layer wafer of claim 1, further comprising interconnection vias between the two heterogeneous wafers of the multi-layer wafer pair.

### Claim 13 (depends on 1)

The multi-layer wafer of claim 1, wherein the multi-layer wafer pair is low temperature bonded to at least one other multi-layer wafer pair to form a multi-layer wafer stack.

### Claim 14 (depends on 1)

The multi-layer wafer of claim 1, wherein the two heterogeneous wafers are low temperature bonded at a temperature range of room temperature to 100° C.

### Claim 15 (depends on 1)

The multi-layer wafer of claim 1, wherein the functionality is greater than or equal to 2 acrylates/molecule.