# US 10,483,213 B2 · Die identification by optically reading selectively blowable fuse elements

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- Number: US 10,483,213 B2
- Document ID: US10483213B2
- Status: Granted
- Kind: B2
- Application number: 15/703,497
- Filed: 2017-09-13
- Published: 2019-03-14
- Granted: 2019-11-19
- Earliest claimed: 2017-09-13
- Assignees: STMicroelectronics S.r.l.
- Applicants: STMicroelectronics S.r.l.
- Inventors: Giona Fucili; Agostino Mirabelli; Lorenzo Papillo
- Web page: https://patentgrep.com/patent/US10483213B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G01R 31/31718: {Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis (mechanical aspects G01R31/2808, G01R31/2851)}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/0611: {Sorting devices}
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers}
- H10W 20/493: {Fuses, i.e. interconnections changeable from conductive to non-conductive}
- G11C 17/16: using electrically-fusible links
- G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)}
- H10P 72/0618: {using identification means, e.g. labels on substrates or labels on containers}
- H10W 46/106: {digital information, e.g. bar codes}
- H10W 46/401: {for identification or tracking}
- H10W 46/601: {for use after dicing}
- H10W 46/603: {Formed on wafers or substrates before dicing and remaining on chips after dicing}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Many integrated circuit die are fabricated on a wafer. Each die includes integrated functional circuitry with an array of fuse elements that are visible to optical inspection. An electrical wafer sort is performed to test the integrated functional circuitry of each die. The array of fuse elements for each die on the wafer are programmed through the electrical wafer sort process with data bits defining a die identification that specifies a location of the die on the wafer. The die is then encapsulated in a package. In the event of package failure, a decapsulation is performed to access the die. Optical inspection of the array of fuse elements is then made to extract the die identification.

## Claims

### Claim 1

An integrated circuit, comprising:
integrated functional circuitry;
an array of fuse elements, each fuse element having a first terminal and a second terminal, wherein the first terminals are directly connected to a fuse sensing node;
a first switch actuated by a first control signal to apply a programming voltage to the fuse sensing node;
a second switch actuated by a second control signal to apply a reading current to the fuse sensing node; and
a demultiplexing circuit comprising:
a switching circuit connected in series with each fuse element within the array of fuse elements at the second terminal; and
a decoder circuit configured to:
selectively actuate the switching circuits in a first mode when the first control signal actuates the first switch and the second switch is deactuated so as to cause the programming voltage to be applied at the fuse sensing node and across selected ones of the fuse elements within the array of fuse elements which is sufficient to blow the selected fuse element so as to program individual fuse elements within the array of fuse elements with data bits defining a die identification that specifies a location of the integrated circuit die on a wafer from which the integrated circuit die was singulated; and
selectively actuate the switching circuits in a second mode when the second control signal actuates the second switch and the first switch is deactuated so as to cause the reading current to be applied at the fuse sensing node and across the fuse elements within the array of fuse elements to generate an output signal at the fuse sensing node indicating whether the fuse element is blown so as to read the data bits defining the die identification.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein the array of fuse elements is located within a region of the integrated circuit die that is not visually obscured from the top surface of the integrated circuit die by any of the following structures: metal lines, vias, bonding pads, capacitor plates, inductor windings.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein the demultiplexer circuit is controlled by a signal received from automated test equipment (ATE) in connection with electrical wafer sort (EWS) processing of the integrated circuit die to selectively blow individual fuse elements within the array of fuse elements to program the data bits defining the die identification.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the decoder circuit receives address bits and decodes the received address bits to selectively actuate the switching circuits.

### Claim 5 (depends on 4)

The integrated circuit of claim 4, wherein the address bits are applied to pins of the integrated circuit die.

### Claim 6 (depends on 4)

The integrated circuit of claim 4, wherein the address bits are serially applied to a pin of the integrated circuit die, further comprises a serial interface configured to serially receive the address bits and output the address bits to the decoder circuit.

### Claim 7

An integrated circuit, comprising:
integrated functional circuitry;
an array of fuse elements, each fuse element having a first terminal and a second terminal, wherein the first terminals are directly connected to a common node;
a first switch actuated by a first control signal to apply a programming voltage to the fuse sensing node;
a second switch actuated by a second control signal to apply a reading current to the fuse sensing node; and
a demultiplexing circuit comprising:
a switching circuit connected in series with each fuse element within the array of fuse elements at the second terminal; and
a decoder circuit configured to:
selectively actuate the switching circuits in a first mode when the first control signal actuates the first switch and the second switch is deactuated so as to cause the programming voltage to be applied at the fuse sensing node and across selected ones of the fuse elements within the array of fuse elements which is sufficient to blow the selected fuse element so as to program individual fuse elements within the array of fuse elements with data bits; and
selectively actuate the switching circuits in a second mode when the second control signal actuates the second switch and the first switch is deactuated so as to cause the reading current to be applied at the fuse sensing node and across the fuse elements within the array of fuse elements to generate an output signal at the common node indicating whether the fuse element is blown so as to read the data bits.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, wherein the array of fuse elements is located within a region of the integrated circuit die that is not visually obscured from the top surface of the integrated circuit die by any of the following structures: metal lines, vias, bonding pads, capacitor plates, inductor windings.

### Claim 9 (depends on 7)

The integrated circuit of claim 7, wherein the demultiplexer circuit is controlled by a signal received from automated test equipment (ATE) in connection with electrical wafer sort (EWS) processing of the integrated circuit die to selectively blow individual fuse elements within the array of fuse elements to program the data bits defining the die identification.

### Claim 10 (depends on 7)

The integrated circuit of claim 7, wherein the decoder circuit receives address bits and decodes the received address bits to selectively actuate the switching circuits.

### Claim 11 (depends on 10)

The integrated circuit of claim 10, wherein the address bits are applied to pins of the integrated circuit die.

### Claim 12 (depends on 10)

The integrated circuit of claim 10, wherein the address bits are serially applied to a pin of the integrated circuit die, further comprises a serial interface configured to serially receive the address bits and output the address bits to the decoder circuit.