# US 10,483,211 B2 · Fan-out package structure and method for forming the same

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- Number: US 10,483,211 B2
- Document ID: US10483211B2
- Status: Granted
- Kind: B2
- Application number: 15/418,896
- Filed: 2017-01-30
- Published: 2017-08-24
- Granted: 2019-11-19
- Earliest claimed: 2016-02-22
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Tzu-Hung Lin; I-Hsuan Peng; Ching-Wen Hsiao; Nai-Wei Liu; Wei-Che Huang
- Web page: https://patentgrep.com/patent/US10483211B2

## CPC

- H10W 70/614: {the multiple chips being integrally enclosed}
- H10D 1/20: Inductors
- H10D 1/47: Resistors having no potential barriers
- H10D 1/68: Capacitors having no potential barriers
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 74/016: {using moulds}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/63: Vias, e.g. via plugs
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto. A first semiconductor die is disposed on and electrically coupled to the first surface of the first RDL structure. A first molding compound is disposed on the first surface of the first RDL structure and surrounds the first semiconductor die. A plurality of solder balls or conductive pillar structures is disposed in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure. A method for forming the semiconductor package is also provided.

## Claims

### Claim 1

A semiconductor package structure, comprising:
a first semiconductor package, comprising:
a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto;
two electronic components respectively disposed on and electrically coupled to the first and second surface of the first RDL structure;
a first semiconductor die disposed on and electrically coupled to the first surface of the first RDL structure;
a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die;
a plurality of screen printed solder balls embedded in the first molding compound and electrically coupled to the first semiconductor die through the first RDL structure;
wherein the first molding compound comprises a plurality of openings to correspondingly expose the plurality of screen printed solder balls;
wherein the semiconductor package structure further comprises a plurality of first conductive structures that fill the plurality of openings and are in contact with the plurality of screen printed solder balls; and
wherein the semiconductor package structure further comprises a second semiconductor package coupled to the first semiconductor package by the plurality of first conductive structures, the second semiconductor package being spaced within 50 microns of the first semiconductor package.

### Claim 2 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein a first electronic component of the two electronic components comprises a capacitor, an inductor, a resistor, or a combination thereof.

### Claim 3 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the first semiconductor package further comprises a plurality of second conductive structures disposed on and electrically coupled to the second surface of the first RDL structure.

### Claim 4 (depends on 1)

The semiconductor package structure as claimed in claim 1,
wherein the second semiconductor package is stacked above the first semiconductor package and wherein the second semiconductor package comprises:
a second RDL structure electrically coupled to the first RDL structure and having a third surface and a fourth surface opposite thereto;
a second semiconductor die disposed on and electrically coupled to the third surface of the second RDL structure; and
a second molding compound disposed on the third surface of the second RDL structure and surrounding the second semiconductor die.

### Claim 5 (depends on 4)

The semiconductor package structure as claimed in claim 4, wherein the second semiconductor package further comprises a third semiconductor die disposed on the second semiconductor die, surrounded by the second molding compound, and electrically coupled to the second RDL structure.

### Claim 6 (depends on 5)

The semiconductor package structure as claimed in claim 5, wherein the second and third semiconductor dies comprise a memory device, respectively.

### Claim 7 (depends on 4)

The semiconductor package structure as claimed in claim 4, wherein the plurality of first conductive structures are disposed on the fourth surface of the second RDL structure extending into the plurality of openings to be electrically coupled between the plurality of screen printed solder balls and the second RDL structure.

### Claim 8

A semiconductor package structure, comprising:
a first semiconductor package, comprising:
a first RDL structure having a first surface and a second surface opposite thereto;
a first semiconductor die disposed on and electrically coupled to the first surface of the first RDL structure;
two electronic components respectively disposed on and electrically coupled to the first and second surface of the first RDL structure;
a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die;
a plurality of screen printed conductive pillar structures disposed in and exposed from the first molding compound, wherein each of the plurality of screen printed conductive pillar structures comprises a metal pillar and a solder material that is bonded between the metal pillar and the first RDL structure such that the plurality of screen printed conductive pillar structures are bonded onto and electrically coupled to the first RDL structure; and
wherein the semiconductor package structure further comprises a second semiconductor package coupled to the first semiconductor package by a plurality of first conductive structures that are in contact with the plurality of screen printed conductive pillar structures, the second semiconductor package being spaced within 50 microns of the first semiconductor package.

### Claim 9 (depends on 8)

The semiconductor package structure as claimed in claim 8, wherein a first electronic component of the two electronic components comprises a capacitor, an inductor, a resistor, or a combination thereof.

### Claim 10 (depends on 8)

The semiconductor package structure as claimed in claim 8, wherein the first semiconductor package further comprises a plurality of second conductive structures disposed on and electrically coupled to the second surface of the first RDL structure.

### Claim 11 (depends on 8)

The semiconductor package structure as claimed in claim 8, wherein the second semiconductor package is stacked above the first semiconductor package and wherein the second semiconductor package comprises:
a second RDL structure electrically coupled to the first RDL structure and having a third surface and a fourth surface opposite thereto;
a second semiconductor die disposed on and electrically coupled to the third surface of the second RDL structure; and
a second molding compound disposed on the third surface of the second RDL structure and surrounding the second semiconductor die.

### Claim 12 (depends on 11)

The semiconductor package structure as claimed in claim 11, wherein the second semiconductor package further comprises a third semiconductor die disposed on the second semiconductor die, surrounded by the second molding compound, and electrically coupled to the second RDL structure.

### Claim 13 (depends on 12)

The semiconductor package structure as claimed in claim 12, wherein the second and third semiconductor dies comprise a memory device, respectively.

### Claim 14 (depends on 11)

The semiconductor package structure as claimed in claim 11, wherein the plurality of first conductive structures are disposed between the fourth surface of the second RDL structure and the exposed plurality of screen printed conductive pillar structures, such that the plurality of first conductive structures are electrically coupled between the plurality of screen printed conductive pillar structures and the second RDL structure.

### Claim 15

A method for forming a semiconductor package structure, comprising:
forming a first semiconductor package structure, comprising:
forming a first RDL structure on a carrier substrate, wherein the first RDL structure has a first surface and a second surface opposite thereto and the second surface of the first RDL structure is attached to the carrier substrate;
screen printing a plurality of solder balls on the first surface of the first RDL structure;
mounting a first semiconductor die and a first electronic component onto the first surface of the first RDL structure, wherein the first semiconductor die is electrically coupled to the plurality of solder balls through the first RDL structure;
forming a first molding compound on the first surface of the first RDL structure, such that the first semiconductor die and the plurality of solder balls are embedded in the first molding compound;
forming a plurality of openings in the first molding compound to correspondingly expose the plurality of solder balls;
removing the carrier substrate from the first RDL structure;
mounting a second electronic component onto the second surface of the first RDL structure after removing the carrier substrate; and
forming a plurality of first conductive structures that fill the plurality of openings and are in contact with the plurality of solder balls; and
coupling a second semiconductor package to the first semiconductor package structure by the plurality of first conductive structures, the second semiconductor package being spaced within 50 microns of the first semiconductor package structure.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein the first electronic component or the second electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof.

### Claim 17 (depends on 15)

The method as claimed in claim 15, further comprising forming a plurality of second conductive structures on the second surface of the first RDL structure.

### Claim 18 (depends on 15)

The method as claimed in claim 15, further comprising:
forming the second semiconductor package, comprising:
forming a second RDL structure above the first molding compound, wherein the second RDL structure has a third surface and a fourth surface opposite thereto and the fourth surface of the second RDL structure faces the first molding compound;
mounting a second semiconductor die on the third surface of the second RDL structure; and
forming a second molding compound on the third surface of the second RDL structure, such that the second semiconductor die is surrounded by the second molding compound.

### Claim 19 (depends on 18)

The method as claimed in claim 18, further comprising forming a third semiconductor die on the second semiconductor die, wherein the third semiconductor die is surrounded by the second molding compound.

### Claim 20 (depends on 19)

The method as claimed in claim 19, wherein the second and third semiconductor dies comprise a memory device, respectively.

### Claim 21 (depends on 18)

The method as claimed in claim 18, further comprising forming the plurality of first conductive structures on the fourth surface of the second RDL structure and in the plurality of openings, such that the plurality of first conductive structures are electrically coupled between the plurality of solder balls and the second RDL structure.

### Claim 22

A method for forming a semiconductor package structure, comprising:
forming a first semiconductor package structure, comprising:
forming a first RDL structure on a carrier substrate, wherein the first RDL structure has a first surface and a second surface opposite thereto and the second surface of the first RDL structure is attached to the carrier substrate;
screen printing a plurality of conductive pillar structures on the first RDL structure, wherein each of the plurality of conductive pillar structures comprises a metal pillar and a solder material that is bonded between the metal pillar and the first RDL structure such that the plurality of conductive pillar structures are bonded onto and electrically coupled to the first RDL structure;
mounting a first semiconductor die and a first electronic component onto the first surface of the first RDL structure, wherein the first semiconductor die is electrically coupled to the plurality of conductive pillar structures through the first RDL structure;
forming a first molding compound on the first surface of the first RDL structure, such that the first semiconductor die and the plurality of conductive pillar structures are in the first molding compound, wherein the plurality of conductive pillar structures is exposed from the first molding compound;
removing the carrier substrate from the first RDL structure; and
mounting a second electronic component onto the second surface of the first RDL structure after removing the carrier substrate; and
coupling a second semiconductor package to the first semiconductor package structure by a plurality of first conductive structures that are in contact with the plurality of conductive pillar structures, the second semiconductor package being spaced within 50 microns of the first semiconductor package structure.

### Claim 23 (depends on 22)

The method as claimed in claim 22 wherein the first electronic component or the second electronic component comprises a capacitor, an inductor, a resistor, or a combination thereof.

### Claim 24 (depends on 22)

The method as claimed in claim 22, further comprising forming a plurality of second conductive structures on the second surface of the first RDL structure.

### Claim 25 (depends on 22)

The method as claimed in claim 22, further comprising:
forming the second semiconductor package, comprising:
forming a second RDL structure above the first molding compound, wherein the second RDL structure has a third surface and a fourth surface opposite thereto and the fourth surface of the second RDL structure faces the first molding compound;
mounting a second semiconductor die on the third surface of the second RDL structure; and
forming a second molding compound on the third surface of the second RDL structure, such that the second semiconductor die is surrounded by the second molding compound.

### Claim 26 (depends on 25)

The method as claimed in claim 25, further comprising forming a third semiconductor die on the second semiconductor die, wherein the third semiconductor die is surrounded by the second molding compound.

### Claim 27 (depends on 26)

The method as claimed in claim 26, wherein the second and third semiconductor dies comprise a memory device, respectively.

### Claim 28 (depends on 25)

The method as claimed in claim 25, further comprising forming the plurality of first conductive structures between the fourth surface of the second RDL structure and the exposed plurality of conductive pillar structures, such that the plurality of first conductive structures are electrically coupled between the plurality of conductive pillar structures and the second RDL structure.