# US 10,483,208 B2 · Interconnection structure, fabricating method thereof, and semiconductor device using the same

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- Number: US 10,483,208 B2
- Document ID: US10483208B2
- Status: Granted
- Kind: B2
- Application number: 15/665,229
- Filed: 2017-07-31
- Published: 2017-12-14
- Granted: 2019-11-19
- Earliest claimed: 2015-09-11
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yu-Hung Lin; Chi-Wen Liu; Horng-Huei Tseng
- Web page: https://patentgrep.com/patent/US10483208B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10W 20/066: {by forming silicides of refractory metals}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

## Claims

### Claim 1

A device comprising:
a multi-gate transistor, the multi-gate transistor including an epitaxial source/drain region;
a dielectric layer overlying the epitaxial source/drain region;
a contact extending through an opening in the dielectric layer and electrically contacting the epitaxial source/drain region, the contact including:
a silicide layer contacting the epitaxial source/drain region, wherein a Si concentration of the silicide is varied along a height of the silicide;
a barrier layer contacting the silicide layer;
a metal layer contacting the barrier layer and contacting sidewalls of the opening in the dielectric layer, wherein the silicide layer is a silicide of the epitaxial source/drain region and the metal layer; and
a conductor contacting the barrier layer, wherein the barrier layer extends between and separates the conductor and the silicide layer.

### Claim 2 (depends on 1)

The device of claim 1, wherein the Si concentration is decreased along the height of the silicide.

### Claim 3 (depends on 1)

The device of claim 1, wherein the Si concentration at an interface between the silicide and the barrier layer is less than that at an interface between the silicide and the epitaxial source/drain region.

### Claim 4 (depends on 1)

The device of claim 1, wherein a material of the silicide comprises TiSi.

### Claim 5 (depends on 1)

The device of claim 1, wherein a material of the silicide comprises TiSiGe, and a Ge concentration is varied along the height of the silicide as the Si concentration.

### Claim 6

A device comprising:
a channel region;
a gate conductor wrapped around the channel region;
a source/drain region on one side of the channel region;
a dielectric layer over the source/drain region, the dielectric layer having an opening therein aligned to the source/drain region;
a portion of the source/drain region forming a silicide layer in the opening;
a metal layer lining sidewalls of the opening, wherein the silicide is a silicide of the source/drain region and the metal layer, and further wherein a silicon concentration of the silicide varies from a top of the silicide layer to a bottom of the silicide layer;
a barrier layer on the metal layer; and
a conductor on the barrier layer and filling the opening.

### Claim 7 (depends on 6)

The device of claim 6, wherein the Si concentration is decreased along the height of the silicide.

### Claim 8 (depends on 6)

The device of claim 6, wherein the Si concentration at an interface between the silicide and the barrier layer is less than that at an interface between the silicide and the source/drain region.

### Claim 9 (depends on 6)

The device of claim 6, wherein a material of the silicide comprises TiSi.

### Claim 10 (depends on 6)

The device of claim 6, wherein a material of the silicide comprises TiSiGe, and a Ge concentration is varied along the height of the silicide as the Si concentration.

### Claim 11 (depends on 6)

The device of claim 6, wherein the metal layer is not present between the barrier layer and the silicide.

### Claim 12 (depends on 6)

The device of claim 6, wherein the metal layer comprises Ti, Co, Ni, Pt, or W.

### Claim 13 (depends on 6)

The device of claim 6, wherein the barrier layer comprises Ta or Ti.

### Claim 14 (depends on 6)

The device of claim 6, wherein the barrier layer is directly in contact with the silicide.

### Claim 15 (depends on 6)

The device of claim 6, wherein the conductor comprises W or Cu.

### Claim 16

A method comprising:
forming a multi-gate transistor structure on a substrate;
covering the multi-gate transistor structure with a dielectric layer;
forming an opening in the dielectric layer, the opening exposing a source/drain region of the multi-gate transistor structure, wherein forming an opening removes a top portion of the source/drain;
lining the opening with a metal layer;
lining the metal layer with a barrier layer;
annealing the source/drain region and the metal layer to form a silicide; and
forming a conductor material atop the silicide and the barrier.

### Claim 17 (depends on 16)

The method of claim 16, wherein a portion of the metal layer between the barrier layer and the source/drain region is reacted with the source/drain region, so that the metal layer is not present between the barrier layer and the silicide.

### Claim 18 (depends on 16)

The method of claim 16, further comprising forming a conductor filling the opening, wherein the conductor is an interconnect structure in the dielectric layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein annealing the source/drain region comprises an annealing temperature and an annealing duration, wherein the annealing temperature is less than 700 degrees Celsius, and wherein the annealing duration is less than 120 seconds.

### Claim 20 (depends on 16)

The method of claim 16, further comprising varying a Si concentration of the silicide along a height of the silicide.