# US 10,483,204 B2 · Logic cell structure with interconnection design and configuration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,204 B2 - Document ID: US10483204B2 - Status: Granted - Kind: B2 - Application number: 15/978,391 - Filed: 2018-05-14 - Published: 2018-09-13 - Granted: 2019-11-19 - Earliest claimed: 2016-12-15 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Fang Chen; Jhon Jhy Liaw; Min-Chang Liang - Web page: https://patentgrep.com/patent/US10483204B2 ## CPC - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) - H10B 10/00: Static random access memory [SRAM] devices - H10B 43/35: with cell select transistors, e.g. NAND - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 84/0172: {Manufacturing their gate conductors} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 89/10: Integrated device layouts - H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/0193: {the components including FinFETs} - H10D 84/853: {comprising FinFETs} - H10D 84/975: {Wiring regions or routing} - H10W 20/033: {in openings in dielectrics} - H10W 20/081: {by forming openings in the dielectric parts} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The semiconductor structure includes a plurality of FETs disposed on a semiconductor substrate, the FETs including gates with elongated shape oriented in a first direction; a first metal layer of first metal lines disposed over the gates and oriented in a second direction perpendicular to the first direction; a second metal layer of second metal lines disposed over the first metal layer and oriented in the first direction; and a third metal layer of third metal lines oriented in the second direction and disposed over the second metal layer. The first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; and the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2. ## Claims ### Claim 1 A semiconductor structure, comprising: a semiconductor substrate; a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction; a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction; a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein the first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; and the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein the plurality of FETs include an n-type conductivity field-effect transistor (nFET) and a p-type conductivity field-effect transistor (pFET) coupled together to form an inverter, wherein the inverter spans a dimension of about 2*P4 along the second direction. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, wherein the plurality of FETs are configured to an NAND gate spanning a dimension of about 3*P4 along the second direction. ### Claim 4 (depends on 1) The semiconductor structure of claim 1, wherein the plurality of FETs are configured to an NOR gate spanning a dimension of about 3*P4 along the second direction. ### Claim 5 (depends on 1) The semiconductor structure of claim 1, wherein the second pitch P2 is less than the first pitch P1 and the third pitch P3. ### Claim 6 (depends on 1) The semiconductor structure of claim 1, wherein the first metal lines have a first thickness T1, the second metal lines have a second thickness T2, the third metal lines have a third thickness T3, and wherein the second thickness T2 is less than the first thickness T1 and the third thickness T3. ### Claim 7 (depends on 6) The semiconductor structure of claim 6, wherein the first thickness and the third thickness are substantially equal to each other. ### Claim 8 (depends on 1) The semiconductor structure of claim 1, wherein the first metal lines have a first width; the second metal lines have a second width; the third metal lines have a third width; and the second width is less than the first width and the third width. ### Claim 9 A semiconductor structure, comprising: a semiconductor substrate; a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction; a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction; a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein the first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2; the FETs include an n-type conductivity field-effect transistor (nFET) and a p-type conductivity field-effect transistor (pFET) coupled together through a common drain to form an inverter, and the inverter spans a dimension of about 2*P4 along the second direction. ### Claim 10 (depends on 9) The semiconductor structure of claim 9, wherein the second pitch P2 is less than the first pitch P1 and the third pitch P3. ### Claim 11 (depends on 9) The semiconductor structure of claim 9, wherein the first metal lines have a first width; the second metal lines have a second width; the third metal lines have a third width; and the second width is less than the first width and the third width. ### Claim 12 (depends on 9) The semiconductor structure of claim 9, wherein the first metal lines have a first thickness; the second metal lines have a second thickness; the third metal lines have a third thickness; and the second thickness is less than the first thickness and the third thickness. ### Claim 13 (depends on 12) The semiconductor structure of claim 12, wherein the first thickness and the third thickness are substantially equal. ### Claim 14 A semiconductor structure, comprising: a semiconductor substrate; a plurality of field-effect transistors (FETs) disposed on the semiconductor substrate, wherein the FETs include gates with elongated shape oriented in a first direction; a first metal layer disposed over the gates, wherein the first metal layer includes a plurality of first metal lines oriented in a second direction perpendicular to the first direction; a second metal layer disposed over the first metal layer, wherein the second metal layer includes a plurality of second metal lines oriented in the first direction; and a third metal layer disposed over the second metal layer, wherein the third metal layer includes a plurality of third metal lines oriented in the second direction, wherein the first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2; the FETs are coupled to a logic gate being one of an NAND gate and an NOR logic gate; and the logic gate spans a dimension of about 3*P4 along the second direction. ### Claim 15 (depends on 14) The semiconductor structure of claim 14, wherein the second pitch P2 is less than the first pitch P1 and the third pitch P3. ### Claim 16 (depends on 14) The semiconductor structure of claim 14, wherein the first metal lines have a first thickness; the second metal lines have a second thickness; the third metal lines have a third thickness; and the second thickness is less than the first thickness and the third thickness. ### Claim 17 (depends on 16) The semiconductor structure of claim 16, wherein the first thickness and the third thickness are substantially equal. ### Claim 18 (depends on 14) The semiconductor structure of claim 14, wherein the first metal lines have a first width; the second metal lines have a second width; the third metal lines have a third width; and the second width is less than the first width and the third width. ### Claim 19 (depends on 5) The semiconductor structure of claim 5, wherein the first pitch P1 and the third pitch P3 are substantially equal with a difference (P3-P1) less than 15% of P1. ### Claim 20 (depends on 7) The semiconductor structure of claim 7, wherein a difference (T1-T3) is less than 15% of T1.