# US 10,483,203 B2 · Semiconductor memory device having pads of varying widths

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- Number: US 10,483,203 B2
- Document ID: US10483203B2
- Status: Granted
- Kind: B2
- Application number: 15/639,316
- Filed: 2017-06-30
- Published: 2018-05-10
- Granted: 2019-11-19
- Earliest claimed: 2016-11-09
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Yung Jun Kim
- Web page: https://patentgrep.com/patent/US10483203B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10D 64/037: {comprising charge-trapping insulators}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10W 20/42: Vias, e.g. via plugs
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided herein is a semiconductor memory device. The semiconductor memory device may include channel layers protruding away from a substrate. The semiconductor memory device may include a plurality of pads respectively coupled to the channel layers. The widths of the pads may or may not be increased depending on a bending of the channel layers.

## Claims

### Claim 1

A semiconductor memory device comprising:
channel layers protruding away from a substrate;
conductive layers configured to enclose the channel layers and stacked on the substrate, the conductive layers extending in a first direction;
a plurality of pads coupled to the channel layers and arranged in the first direction; and
a plurality of bit lines coupled to the channel layers through the plurality of pads,
wherein a pad of the plurality of pads has a width in the first direction so that the pad is wider relative to a preceding pad of the plurality of pads, and
wherein the channel layers are directly connected to the pads, respectively.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the conductive layers extend in the first direction and form a stepwise structure.

### Claim 3 (depends on 2)

The semiconductor memory device according to claim 2, wherein the pads increases in width toward the stepwise structure.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1, wherein the width of each of the pads with respect to the first direction is greater than a width of the preceding pad in the first direction.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein widths of the pads with respect to a second direction intersecting the first direction are the same as each other.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein upper ends of the channel layers are coupled with lower portions of the respective pads.

### Claim 7 (depends on 6)

The semiconductor memory device according to claim 6, wherein the width of each of the pads with respect to the first direction or a width of each of the pads with respect to a second direction intersecting the first direction are greater than widths of the upper ends of the channel layers.

### Claim 8 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
contact plugs coupled to the pads and arranged in the first direction.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8, wherein lower ends of the contact plugs are coupled with upper portions of the respective pads.

### Claim 10 (depends on 9)

The semiconductor memory device according to claim 9, wherein the width of each of the pads with respect to the first direction or a width of each of the pads with respect to a second direction intersecting the first direction are greater than widths of the lower ends of the contact plugs.

### Claim 11 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
a source line disposed in the same layer as the pads.

### Claim 12 (depends on 2)

The semiconductor memory device according to claim 2, further comprising:
interlayer insulating layers configured to enclose the channel layers and alternately stacked with the conductive layers on the substrate, the interlayer insulating layers extending in the first direction and forming the stepwise structure; and
an insulating layer configured to cover the stepwise structure.

### Claim 13 (depends on 1)

The semiconductor memory device according to claim 1, further comprising:
multilayer layers disposed between the channel layers and the conductive layers, and configured to enclose the channel layers.

### Claim 14 (depends on 2)

The semiconductor memory device according to claim 2,
wherein the channel layers are formed in a cell array region,
wherein the stepwise structure is formed in a word line contact region making contact with one side of the cell array region, and
wherein the pads increase in width toward the word line contact region.

### Claim 15 (depends on 8)

The semiconductor memory device according to claim 8, wherein the bit lines are coupled to the contact plugs and arranged in the first direction.

### Claim 16 (depends on 15)

The semiconductor memory device according to claim 15, wherein upper ends of the contact plugs are coupled with lower portion of the bit lines.

### Claim 17 (depends on 15)

The semiconductor memory device according to claim 15, wherein the bit lines extend in a second direction intersecting the first direction.

### Claim 18

A semiconductor memory device comprising:
a plurality of bit lines;
a source line;
channel layers coupled between the plurality of bit lines and the source line; and
pads arranged on the channel layers, wherein the channel layers are directly connected to the pads, respectively,
wherein the plurality of bit lines are coupled to the channel layers through the pads, and
wherein the pads include a first pad disposed at a medial portion, a second pad disposed at a first outermost position and a third pad disposed at a second outermost position, and a width of the second pad or the third pad is greater than a width of the first pad.

### Claim 19 (depends on 18)

The semiconductor memory device according to claim 18, wherein distances between a word line contact region and the pads are reduced from the pad that is disposed at the medial portion toward at least one of the pad that is disposed at the first outermost position and the pad that is disposed at the second outermost position.

### Claim 20 (depends on 19)

The semiconductor memory device according to claim 19,
wherein the channel layers are formed in a cell array region, and
wherein the word line contact region makes contact with at least one side of the cell array region.

### Claim 21 (depends on 18)

The semiconductor memory device according to claim 18, wherein the width of the second pad is substantially symmetrical with the width of the third pad with reference to the first pad.

### Claim 22 (depends on 18)

The semiconductor memory device according to claim 18, wherein a width of each of the pads between the first outermost position and the first pad is substantially symmetrical with a width of each of the pads between the second outermost position and the first pad.

### Claim 23

A semiconductor memory device comprising:
contact plugs;
channel layers protruding away from a substrate; and
a plurality of pads respectively coupled between the contact plugs and channel layers,
wherein the pads have a greater width as a bending of the channel layers or the contact plugs increases.

### Claim 24 (depends on 23)

The semiconductor memory device according to claim 23, wherein at least one pad from the plurality of pads has a greater width than another pad from the plurality of pads.

### Claim 25 (depends on 24)

The semiconductor memory device according to claim 24, wherein the at least one pad from the plurality of pads has substantially the same width as the another pad from the plurality of pads.

### Claim 26 (depends on 23)

The semiconductor memory device according to claim 23, further comprising:
conductive layers configured to enclose the channel layers and stacked on the substrate, the conductive layers extending in a first direction,
wherein the pads are arranged in the first direction, and
wherein the pads increase in width in the first direction so that each of the pads is wider relative to a preceding pad.