# US 10,483,199 B2 · Semiconductor device with coils in different wiring layers

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- Number: US 10,483,199 B2
- Document ID: US10483199B2
- Status: Granted
- Kind: B2
- Application number: 16/048,408
- Filed: 2018-07-30
- Published: 2018-11-22
- Granted: 2019-11-19
- Earliest claimed: 2017-06-07
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Takayuki Igarashi; Takuo Funaya
- Web page: https://patentgrep.com/patent/US10483199B2

## CPC

- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/4405: {the principal metal being aluminium}
- H10W 70/411: {Chip-supporting parts, e.g. die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 72/90: Bond pads, in general
- H10W 90/00: Package configurations
- H10W 90/811: {Multiple chips on leadframes}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a wiring M3 formed on an interlayer insulator IL3, and a coil CL2 and a wiring M4 formed on the interlayer insulator IL4. Moreover, a distance DM4 between the coil CL2 and the wiring M4 is longer than a distance DM3 between the coil CL2 and the wiring M3 (DM4>DM3). Furthermore, the distance DM3 between the coil CL2 and the wiring M3 is set to be longer than a sum of a film thickness of the interlayer insulator IL3 and a film thickness of the interlayer insulator IL4, which are positioned between the coil CL1 and the coil CL2. In this manner, it is possible to improve an insulation withstand voltage between the coil CL2 and the wiring M4 or the like, where a high voltage difference tend to occur. Moreover, a transformer formation region 1A and a seal ring formation region 1C surrounding a peripheral circuit formation region 1B are formed so as to improve the moisture resistance.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having a main surface and a rear surface opposite the main surface;
a first insulating film formed on the main surface of the substrate;
a first coil formed on the first insulating film;
a second insulating film formed on the first coil;
a first wiring formed on the second insulating film;
a third insulating film formed on the first wiring;
a groove formed in the third insulating film and separating the third insulating film into a first portion of the third insulating film and a second portion of the third insulating film in a plan view;
a second coil formed on the first portion of the third insulating file and overlapped with the first coil in a cross section view; and
a second wiring formed on the second portion of the third insulating film and in the groove,
wherein the groove surrounds the first and second coils in the plan view, and
wherein the groove overlaps with the first wiring in the cross section view.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the first wiring surrounds the first and second coils in the plan view.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2,
wherein the second wiring surrounds the first and second coils in the plan view, and
wherein the first wiring is connected to the second wiring in the groove in the cross section view.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein a thickness of the second wiring is greater than a thickness of the first wiring in a thickness direction of the substrate in the cross section view.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4,
wherein a thickness of the second coil is greater than a thickness of the first coil in the thickness direction of the substrate in the cross section view.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5,
wherein a thickness of the third insulating film is greater than a thickness of the second insulating film in the thickness direction of the substrate in the cross section view, and
wherein a depth of the groove is greater than a thickness of the first wiring in the thickness direction of the substrate in the cross section view.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein each of the second insulating film and the third insulating film is formed of an inorganic insulating film.

### Claim 8

A semiconductor device comprising:
a substrate having a main surface and a rear surface opposite the main surface;
a first insulating film formed on the main surface of the substrate;
a first coil formed on the first insulating film;
a second insulating film formed on the first coil;
a first wiring formed on the second insulating film;
a third insulating film formed on the first wiring;
a groove formed in the third insulating film and separating the third insulating film into a first portion of the third insulating film and a second portion of the third insulating film in a plan view;
a second coil formed on the first portion of the third insulating file and overlapped with the first coil in a cross section view; and
a second wiring formed on the second portion of third insulating film and in the groove,
wherein each of the groove, the first wiring and the second wiring surrounds the first and second coils in the plan view,
wherein the second wiring overlaps with the first wiring and the groove in the cross section view, and
wherein the first wiring separates the third insulating film in the first portion of the third insulating film and the second portion of the third insulating film in the cross section view.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8,
wherein the first wiring is connected to the second wiring in the groove in the cross section view.

### Claim 10 (depends on 8)

The semiconductor device according to claim 8,
wherein a thickness of the second wiring is greater than a thickness of the first wiring in a thickness direction of the substrate in the cross section view.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10,
wherein a thickness of the second coil is greater than a thickness of the first coil in the thickness direction of the substrate in the cross section view.

### Claim 12 (depends on 8)

The semiconductor device according to claim 8,
wherein a thickness of the third insulating film is greater than a thickness of the second insulating film in the thickness direction of the substrate in the cross section view.

### Claim 13 (depends on 12)

The semiconductor device according to claim 12,
wherein a depth of the groove is greater than a thickness of the first wiring in the thickness direction of the substrate in the cross section view.

### Claim 14 (depends on 8)

The semiconductor device according to claim 8,
wherein each of the second insulating film and the third insulating film is formed of an inorganic insulating film.