# US 10,483,196 B2 · Embedded trace substrate structure and semiconductor package structure including the same

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- Number: US 10,483,196 B2
- Document ID: US10483196B2
- Status: Granted
- Kind: B2
- Application number: 15/887,780
- Filed: 2018-02-02
- Published: 2018-08-23
- Granted: 2019-11-19
- Earliest claimed: 2017-02-22
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Advanced Semiconductor Engineering, Inc.
- Inventors: Yu-Ying Lee
- Web page: https://patentgrep.com/patent/US10483196B2

## CPC

- H10W 70/65: Shapes or dispositions of interconnections
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/095: {of vias therein}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 74/016: {using moulds}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/07255: {changes in materials}
- H10W 72/073: {of die-attach connectors}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/2528: {Intermetallic compounds}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.

## Claims

### Claim 1

A substrate structure, comprising:
a carrier having a first surface and a second surface;
a first metal layer disposed on the first surface of the carrier, wherein the first metal layer includes a base metal layer and a conductive metal layer, the base metal layer is disposed on the first surface of the carrier, and the conductive metal layer is disposed on the base metal layer;
a circuit layer disposed on the conductive metal layer of the first metal layer; and
a dielectric layer covering the circuit layer and defining a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.

### Claim 2 (depends on 1)

The substrate structure of claim 1, wherein a first surface of the circuit layer is recessed from a first surface of the dielectric layer.

### Claim 3 (depends on 1)

The substrate structure of claim 1, wherein a surface roughness (Ra) of a second surface of the dielectric layer is greater than about 0.15 micrometers (μm).

### Claim 4 (depends on 1)

The substrate structure of claim 1, wherein a thickness of the circuit layer is in a range of about 10 μm to about 15 μm, and a line width and a line space (L/S) of the circuit layer is in a range of about 5 μm/about 5 μm to about 12 μm/about 12 μm.

### Claim 5 (depends on 1)

The substrate structure of claim 1, wherein a size of at least one opening of the plurality of openings of the dielectric layer is in a range of about 40 μm*about 40 μm to about 80 μm*about 80 μm.

### Claim 6 (depends on 1)

The substrate structure of claim 1, further comprising a second metal layer disposed on the second surface of the carrier.

### Claim 7

A semiconductor package structure, comprising:
a circuit layer having a first surface and a second surface;
a dielectric layer covering the first surface of the circuit layer and having a first surface and a second surface, wherein the dielectric layer defines an opening to expose a portion of the circuit layer, and the opening extends through the dielectric layer;
a semiconductor die attached to the circuit layer by flip chip bonding;
a connecting element electrically connecting the semiconductor die and the circuit layer, wherein at least a portion of the connecting element is disposed in the opening of the dielectric layer and is exposed from the second surface of the dielectric layer; and
a protection layer disposed on the second surface of the dielectric layer to cover the circuit layer, wherein the protection layer defines a plurality of openings to expose portions of the second surface of the circuit layer.

### Claim 8 (depends on 7)

The semiconductor package structure of claim 7, wherein the second surface of the circuit layer is exposed from the second surface of the dielectric layer, and the circuit layer does not protrude from the second surface of the dielectric layer.

### Claim 9 (depends on 7)

The semiconductor package structure of claim 7, wherein a material of the connecting element includes tin, a bottom portion of the connecting element is exposed from the second surface of the dielectric layer, and the bottom portion of the connecting element includes an intermetallic compound (IMC).

### Claim 10 (depends on 9)

The semiconductor package structure of claim 9, wherein the IMC includes a combination of copper and tin.

### Claim 11 (depends on 7)

The semiconductor package structure of claim 7, wherein a surface of the connecting element is coplanar with the second surface of the dielectric layer, and the second surface of the circuit layer is recessed from the second surface of the dielectric layer.

### Claim 12 (depends on 7)

The semiconductor package structure of claim 7, wherein a surface roughness (Ra) of a surface of the connecting element is greater than a surface roughness (Ra) of the second surface of the circuit layer.

### Claim 13 (depends on 7)

The semiconductor package structure of claim 7, wherein the protection layer contacts an inner side surface of the connecting element.

### Claim 14 (depends on 7)

The semiconductor package structure of claim 7, wherein a material of the protection layer is the same as a material of the dielectric layer.

### Claim 15 (depends on 7)

The semiconductor package structure of claim 7, further comprising an encapsulant covering the semiconductor die and the dielectric layer.

### Claim 16 (depends on 7)

The semiconductor package structure of claim 7, wherein a surface roughness (Ra) of the second surface of the dielectric layer is greater than about 0.15 μm.

### Claim 17 (depends on 7)

The semiconductor package structure of claim 7, wherein the circuit layer consists of a single layer.

### Claim 18 (depends on 17)

The semiconductor package structure of claim 17, wherein the circuit layer includes a solder bump land pad, and the semiconductor package structure further comprises an external connector connected to the solder bump land pad.