# US 10,483,194 B2 · Interposer substrate and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,194 B2 - Document ID: US10483194B2 - Status: Granted - Kind: B2 - Application number: 15/997,849 - Filed: 2018-06-05 - Published: 2018-10-04 - Granted: 2019-11-19 - Earliest claimed: 2014-12-03 - Assignees: Phoenix Pioneer Technology Co., Ltd. - Applicants: Phoenix Pioneer Technology Co., Ltd. - Inventors: Pao-Hung Chou; Shih-Ping Hsu - Web page: https://patentgrep.com/patent/US10483194B2 ## CPC - H10W 70/685: comprising multiple insulating layers - H05K 1/0296: {Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18)} - H05K 1/111: {Pads for surface mounting, e.g. lay-out} - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) - H10W 70/68: Shapes or dispositions thereof - H05K 1/0284: {Details of three-dimensional rigid printed circuit boards (H05K1/119 takes precedence; shaping of the substrate H05K3/0014)} - H05K 1/0298: {Multilayer circuits} - H05K 3/061: {Etching masks} - H05K 3/40: Forming printed elements for providing electric connections to or between printed circuits - H05K 2201/10378: Interposers - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 70/095: {of vias therein} - H10W 70/635: {Through-vias} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract The invention provides an interposer substrate and a method of fabricating the same. The method includes: etching a carrier to form a recessed groove thereon; filling a dielectric material in the recessed groove to form a first dielectric material layer, or forming a patterned first dielectric material layer on the carrier; forming a first wiring layer, a first conductive block and a second dielectric material layer on the carrier and the first dielectric material layer sequentially, with the first wiring layer and the first conductive block embedded in the second dielectric material layer; and forming a second wiring layer and a second conductive block on the second dielectric material layer. A coreless interposer substrate having fine pitches is thus fabricated. ## Claims ### Claim 1 An interposer substrate, comprising: a second dielectric material layer having opposing first and second surfaces; a first wiring layer embedded in the second dielectric material layer and exposed from the first surface of the second dielectric material layer; a first dielectric material layer formed on the first surface of the second dielectric material layer and the first wiring layer, wherein a portion of the first wiring layer extends continuously into the first dielectric material layer from the second dielectric material layer, and the first dielectric material layer has a plurality of openings, from which a portion of the first wiring layer is exposed; a plurality of first conductive blocks embedded in the second dielectric material layer and having first terminal surfaces connected to the first wiring layer and second terminal surfaces opposing to the first terminal surfaces and flush with the second surface of the second dielectric material layer; a second wiring layer formed on the second surface of the second dielectric material layer and having a first side connected to the second terminal surfaces of the first conductive blocks and a second side opposing to the first surface of the second wiring layer; a plurality of second conductive blocks formed on the second side of the second wiring layer; and an insulative protection layer formed on the second surface of the second dielectric material layer, the second wiring layer and the second conductive blocks, wherein an end of the second conductive blocks is exposed from the insulative protection layer, and the insulative protection layer has at least a concave portion formed between two of the second conductive blocks. ### Claim 2 (depends on 1) The interposer substrate of claim 1, further comprising a frame-type carrier formed on the first dielectric material layer. ### Claim 3 (depends on 1) The interposer substrate of claim 1, wherein the portion of the first wiring layer exposed from the openings of the first dielectric material layer serves as bonding pads, for an external electronic component to be disposed on and electrically connected with the bonding pads via a plurality of conductive elements. ### Claim 4 (depends on 1) The interposer substrate of claim 1, wherein the first wiring layer has a first portion embedded in the second dielectric material layer and a second portion formed in the openings of the first dielectric material layer. ### Claim 5 (depends on 1) The interposer substrate of claim 1, wherein the first wiring layer having a surface flush with the first surface of the second dielectric material layer.