# US 10,483,193 B2 · Electrical connectivity for circuit applications

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- Number: US 10,483,193 B2
- Document ID: US10483193B2
- Status: Granted
- Kind: B2
- Application number: 16/247,941
- Filed: 2019-01-15
- Published: 2019-05-16
- Granted: 2019-11-19
- Earliest claimed: 2010-07-06
- Assignees: Infineon Technologies Americas Corp.
- Applicants: Infineon Technologies Americas Corp.
- Inventors: Donald J. Desbiens; Gary D. Polhemus; Robert T. Carroll
- Web page: https://patentgrep.com/patent/US10483193B2

## CPC

- H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 70/041: {Connecting or disconnecting interconnections to or from leadframes, e.g. connecting bond wires or bumps}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/726: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

According to example configurations herein, a leadframe includes a first conductive strip, a second conductive strip, and a third conductive strip disposed substantially adjacent and substantially parallel to each other. A semiconductor chip substrate includes a first array of switch circuits disposed adjacent and parallel to a second array of switch circuits. Source nodes in switch circuits of the first array are disposed substantially adjacent and substantially parallel to source nodes in switch circuits of the second array. When the semiconductor chip and the leadframe device are combined to form a circuit package, a connectivity interface between the semiconductor chip and conductive strips in the circuit package couples each of the source nodes in switch circuits of the first array and each of the multiple source nodes in switch circuits of the second array to a common conductive strip in the leadframe device.

## Claims

### Claim 1

A method comprising:
aligning a face of a chip substrate with respect to an electrically conductive surface of a host substrate, the chip substrate fabricated to include first switch circuits and second switch circuits, a sequence of nodes of the second switch circuits disposed on the face of the chip substrate alongside and substantially parallel to a sequence of nodes of the first switch circuits; and
coupling the sequence of nodes of the first switch circuits and the sequence of nodes of the second switch circuits to an electrically conductive surface of the host substrate.

### Claim 2 (depends on 1)

The method as in claim 1, wherein the electrically conductive surface is a lengthwise conductive strip disposed on the face of the host substrate to which the sequence of nodes of the first switch circuits and the sequence of nodes of the second switch circuits are coupled.

### Claim 3 (depends on 1)

The method as in claim 1, wherein the first switch circuits are disposed as a first row of transistor circuits on the chip substrate; and
wherein the second switch circuits are disposed as a second row of transistor circuits on the chip substrate.

### Claim 4 (depends on 1)

The method as in claim 1, wherein the first switch circuits are disposed alongside the second switch circuits.

### Claim 5 (depends on 1)

The method as in claim 1, wherein the sequence of nodes of the first switch circuits is a first set of nodes, the first switch circuits including a second set of nodes, the first set of nodes disposed alongside the second set of nodes on the chip substrate;
wherein the sequence of nodes of the second switch circuits is a third set of nodes; and
wherein the first set of nodes is disposed on the chip substrate alongside and between the second set of nodes and the third set of nodes.

### Claim 6 (depends on 1)

The method as in claim 1, wherein the sequence of nodes of the first switch circuits in contact with the electrically conductive surface are drain nodes;
wherein the sequence of nodes of the second switch circuits in contact with the electrically conductive surface are drain nodes; and
wherein a combination of the drain nodes of the first switch circuits and the drain nodes of the second switch circuits are disposed between a set of source nodes of the first switch circuits and a set of source nodes of the second switch circuits.

### Claim 7 (depends on 1)

The method as in claim 1, wherein the sequence of nodes of the first switch circuits in contact with the electrically conductive surface are source nodes;
wherein the sequence of nodes of the second switch circuits in contact with the electrically conductive surface are source nodes; and
wherein a combination of the source nodes of the first switch circuits and the source nodes of the second switch circuits are disposed between a set of drain nodes of the first switch circuits and a set of drain nodes of the second switch circuits.

### Claim 8 (depends on 1)

The method as in claim 1, wherein the chip substrate includes multiple rows of switch circuits;
wherein the first switch circuits reside in a first row of the multiple rows on the chip substrate; and
wherein the second switch circuits reside in a second row of the multiple rows of the chip substrate, the second row adjacent and parallel to the first row.

### Claim 9 (depends on 1)

The method as in claim 1, wherein the first switch circuits are a first sequence of switch circuit tiles on the chip substrate;
wherein the second switch circuits are a second sequence of switch circuit tiles on the chip substrate; and
wherein the first sequence of switch circuits is disposed parallel and adjacent to the second sequence of switch circuits on the chip substrate, the sequence of nodes of the second switch circuits disposed next to the sequence of nodes of the first switch circuits.

### Claim 10 (depends on 1)

The method as in claim 1, wherein the electrically conductive surface is a strip of conductive material disposed in an electronic circuit package.

### Claim 11 (depends on 1)

The method as in claim 1, wherein the sequence of nodes of the first switch circuits in contact with the electrically conductive surface are source nodes;
wherein the sequence of nodes of the second switch circuits in contact with the electrically conductive surface are source nodes; and
wherein a combination of the source nodes of the first switch circuits and the source nodes of the second switch circuits is disposed between a row of drain nodes of the first switch circuits and a row of drain nodes of the second switch circuits.

### Claim 12 (depends on 1)

The method as in claim 1, wherein the chip substrate is fabricated to include third switch circuits disposed on the host substrate, source nodes of the second switch circuits disposed on the chip substrate alongside source nodes of the third switch circuits.

### Claim 13 (depends on 12)

The method as in claim 12, wherein the second switch circuits are disposed on the chip substrate between the first switch circuits and the third switch circuits.

### Claim 14 (depends on 1)

The method as in claim 1, wherein each of the first switch circuits is electrically isolated from each other prior to coupling of the chip substrate to the electrically conductive surface of the host substrate; and
wherein each of the second switch circuits is electrically isolated from each other prior to coupling of the chip substrate to the electrically conductive surface of the host substrate.

### Claim 15 (depends on 1)

The method as in claim 1 further comprising:
fabricating the chip substrate and the host substrate in an electronic circuit package in which the electrically conductive surface is an electrically conductive strip.

### Claim 16 (depends on 4)

The method as in claim 4, wherein the sequence of nodes of the first switch circuits is disposed side-by-side with respect to the sequence of nodes of the second switch circuits.

### Claim 17 (depends on 1)

The method as in claim 1, wherein a sequence of drain nodes of the first switch circuits and a sequence of drain nodes of the second switch circuits are disposed nearer to each other than a sequence of source nodes of the first switch circuits and a sequence of source nodes of the second switch circuits.

### Claim 18 (depends on 1)

The method as in claim 1, wherein a sequence of source nodes of the first switch circuits and a sequence of source nodes of the second switch circuits are disposed nearer to each other than a sequence of drain nodes of the first switch circuits and a sequence of drain nodes of the second switch circuits.

### Claim 19 (depends on 1)

The method as in claim 1, wherein the chip substrate includes a first transistor circuit tile, a second transistor circuit tile, a third transistor circuit tile, a fourth transistor circuit tile, a fifth transistor circuit tile, and a sixth transistor circuit tile;
wherein the first switch circuits are a first sequence of transistor circuit tiles on the chip substrate, the first sequence of transistor circuit tiles including the first transistor circuit tile, the second transistor circuit tile, and the third transistor circuit tile; and
wherein the second switch circuits are a second sequence of transistor circuit tiles on the chip substrate, the second sequence of transistor circuit tiles including the fourth transistor circuit tile, the fifth transistor circuit tile, and the sixth transistor circuit tile.

### Claim 20 (depends on 19)

The method as in claim 19, wherein each of the first switch circuits includes multiple transistors connected in parallel;
wherein each of the second switch circuits includes multiple transistors connected in parallel;
wherein each of the transistor circuit tiles in the first sequence are electrically isolated from each other prior to the chip substrate being affixed to the host substrate; and
wherein each of the transistor circuit tiles in the second sequence are electrically isolated from each other prior to the chip substrate being affixed to the host substrate.