# US 10,483,188 B2 · Compensation of an arc curvature generated in a wafer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,188 B2 - Document ID: US10483188B2 - Status: Granted - Kind: B2 - Application number: 16/062,902 - Filed: 2016-12-14 - Published: 2018-12-20 - Granted: 2019-11-19 - Earliest claimed: 2015-12-15 - Assignees: Commissariat A L'energie Atomique Et Aux Energies Alternatives - Applicants: Commissariat à L'energie Atomique Et Aux Energies Alternatives - Inventors: Abdenacer Ait-Mani; Bertrand Chambion - Web page: https://patentgrep.com/patent/US10483188B2 ## CPC - H10W 40/253: {Semiconductors} - H10P 14/2925: {Surface structures} - H10P 14/38: {characterised by treatments done after the formation of the materials} - H10P 90/12: {Preparing bulk and homogeneous wafers} - H10W 20/056: {by filling conductive material into holes, grooves or trenches} - H10W 20/098: {by filling between adjacent conductive parts} - H10P 10/128: {by direct semiconductor to semiconductor bonding} - H10P 90/1914: {using bonding} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract This method comprises the steps of: a) forming a set of first trenches on the first surface of the wafer; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a CTE α1; d) filling the second trenches with a second material having a CTE α2, and verifying α2>α0 or α2<α0 depending on whether the first material verifies α1>α0 or α1<α0. ## Claims ### Claim 1 Method for performing compensation of a bow generated in a wafer made from a material, the wafer comprising opposite first and second surfaces, the material of the wafer having a coefficient of thermal expansion noted α0; the method comprising the steps of: a) forming a set of first trenches on the first surface of the wafer, the first surface being designed to comprise electronic components; b) forming a set of second trenches on the second surface of the wafer, at least partially facing the first trenches; c) filling the first trenches with a first material having a coefficient of thermal expansion α1; d) filling the second trenches with a second material having a coefficient of thermal expansion α2, and verifying α2>α0 or α2<α0 depending on whether the first material verifies α1>α0 or α1<α0, wherein step a) is executed in such a way that first trenches of the set of first trenches define a cutting path of the wafer and step b) is executed in such a way that the set of second trenches are totally facing said first trenches of the set of first trenches. ### Claim 2 (depends on 1) Method according to claim 1, wherein the first and second materials respectively occupy a first volume V1 and a second volume V2 inside the first and second trenches on completion of steps c) and d); and step d) is executed in such a way that V 2 = V 1 ×  α 0 - α 1   α 0 - α 2  . ### Claim 3 (depends on 1) Method according to claim 1, wherein the first and second trenches respectively present a first form factor Φ1 and a second form factor Φ2 in steps a) and b), defined as the ratio between the width and depth of the corresponding trenches; and step b) is executed in such a way that Φ2=Φ1±20%. ### Claim 4 (depends on 3) Method according to claim 3, wherein step b) is executed in such a way that Φ2=Φ1±15%, or Φ2=Φ1±10%. ### Claim 5 (depends on 1) Method according to claim 1, comprising a step a1) consisting in coating the first trenches with a dielectric layer before step c), the dielectric layer preferentially being an oxide layer. ### Claim 6 (depends on 1) Method according to claim 1, comprising a step b1) consisting in coating the second trenches with a dielectric layer before step d), the dielectric layer preferentially being an oxide layer. ### Claim 7 (depends on 6) Method according to claim 6, wherein steps a1) and b1) are concomitant. ### Claim 8 (depends on 1) Method according to claim 1, wherein step d) is executed in such a way that the second material is identical to the first material, steps c) and d) preferably being concomitant. ### Claim 9 (depends on 1) Method according to claim 1, comprising: a step c1) consisting in planarizing the first material so as to be flush with the first surface after step c); and preferably a step d1) consisting in planarizing the second material so as to be flush with the second surface after step d). ### Claim 10 (depends on 1) Method according to claim 1, wherein the first and second materials are selected from the group comprising polycrystalline silicon, a polyimide, a polyepoxide, an acrylic, an oxide, a nitride, and a glass. ### Claim 11 (depends on 1) Method according to claim 1, wherein the material of the wafer is selected from the group comprising a semiconductor material, a ceramic, a glass, and sapphire; the semiconductor material preferably being silicon-based. ### Claim 12 Structure for performing compensation of a bow, comprising: a wafer made from a material, comprising opposite first and second surfaces, the material of the wafer having a coefficient of thermal expansion noted α0; a set of first trenches formed on the first surface and filled with a first material having a coefficient of thermal expansion α1; a set of second trenches formed on the second surface, at least partially facing the first trenches and filled with a second material having a coefficient of thermal expansion α2, and verifying α2>α0 or α2<α0 depending on whether the first material verifies α1>α0 or α1<α0 , wherein first trenches of the set of first trenches define a cutting path of the wafer and the set of second trenches are totally facing said first trenches of the set of first trenches. ### Claim 13 (depends on 12) Structure according to claim 12, wherein the first and second materials respectively occupy a first volume V1 and a second volume V2 inside the first and second trenches and verifying V 2 = V 1 ×  α 0 - α 1   α 0 - α 2  . ### Claim 14 (depends on 12) Structure according to claim 12, wherein the first and second trenches respectively present a first form factor Φ1 and a second form factor Φ2, defined as the ratio between the width and depth of the corresponding trenches; and verifying Φ2=Φ1±20%, preferably Φ2=Φ1±15%, more preferentially Φ2=Φ1±10%. ### Claim 15 (depends on 12) Structure according to claim 12, wherein the first trenches are coated with a dielectric layer inserted between the material of the wafer and the first material; and the second trenches are preferably coated with a dielectric layer inserted between the material of the wafer and the second material. ### Claim 16 (depends on 12) Structure according to claim 12, wherein the first material is flush with the first surface; and preferably the second material is flush with the second surface. ### Claim 17 (depends on 1) Method according to claim 1, wherein the set of first trenches comprises primary first trenches and secondary first trenches, the primary first trenches being deeper than secondary first trenches and wherein the primary first trenches define the cutting path and the secondary first trenches are arranged to electrically insulate electronic components on first surface of wafer. ### Claim 18 (depends on 12) Structure according to claim 12, wherein the set of first trenches comprises primary first trenches and secondary first trenches, the primary first trenches being deeper than secondary first trenches and wherein the primary first trenches define the cutting path and the secondary first trenches are arranged to electrically insulate electronic components on first surface of wafer.