# US 10,483,187 B2 · Heat spreading device and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,187 B2 - Document ID: US10483187B2 - Status: Granted - Kind: B2 - Application number: 15/800,349 - Filed: 2017-11-01 - Published: 2019-01-03 - Granted: 2019-11-19 - Earliest claimed: 2017-06-30 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Chen-Hua Yu; Wensen Hung; Ming-Fa Chen; Tsung-Yu Chen - Web page: https://patentgrep.com/patent/US10483187B2 ## CPC - H10W 40/253: {Semiconductors} - H10P 72/74: {using temporarily an auxiliary support} - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04) - H10W 90/00: Package configurations - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10P 72/7416: {used during dicing or grinding} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10W 40/258: {Metallic materials (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10W 40/70: Fillings or auxiliary members in containers or in encapsulations for thermal protection or control - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 72/01223: {in liquid form, e.g. by dispensing droplets or by screen printing} - H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping} - H10W 72/01235: {by plating, e.g. electroless plating or electroplating} - H10W 72/01238: {in gaseous form, e.g. by CVD or PVD} - H10W 72/01257: {by reflowing} - H10W 72/0198: {batch processes} - H10W 72/072: {of bump connectors} - H10W 72/07252: {changes in structures or sizes} - H10W 72/07254: {changes in dispositions} - H10W 72/073: {of die-attach connectors} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/265: {Providing thermal transfer, e.g. thermal bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 72/9445: {Top-view layouts, e.g. mirror arrays} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 72/965: {Providing thermal transfer} - H10W 72/967: {Multiple bond pads having different functions} - H10W 74/014: {using batch processing} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape - H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/792: {between multiple chips} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract In an embodiment, a device includes: an integrated circuit die having a first side and a second side opposite the first side; a die stack on the first side of the integrated circuit die; a dummy semiconductor feature on the first side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die; a first adhesive disposed between the die stack and the dummy semiconductor feature; and a plurality of conductive connectors on the second side of the integrated circuit die. ## Claims ### Claim 1 A method comprising: placing a die stack on a front side of a device wafer; forming conductive connectors on a back side of the device wafer; singulating the device wafer to form an integrated circuit die, the die stack disposed on the integrated circuit die; placing the integrated circuit die on a carrier substrate; bonding a front side of a dummy wafer to the integrated circuit die, the die stack disposed in a recess in the front side of the dummy wafer; debonding the integrated circuit die from the carrier substrate; and singulating the dummy wafer to form a dummy semiconductor feature, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die. ### Claim 2 (depends on 1) The method of claim 1 further comprising: before the singulating the dummy wafer, thinning a back side of the dummy wafer until the recess is exposed, thereby forming an opening extending through the dummy wafer; and forming an adhesive in the opening, top surfaces of the adhesive, the dummy wafer, and the die stack being level. ### Claim 3 (depends on 1) The method of claim 1 further comprising: before the bonding the front side of the dummy wafer to the integrated circuit die, forming an adhesive on the die stack; and placing the front side of the dummy wafer on the integrated circuit die, the adhesive filling the recess. ### Claim 4 (depends on 1) The method of claim 1 further comprising: bonding the integrated circuit die to a package substrate with the conductive connectors; forming an underfill between the package substrate and the integrated circuit die, the underfill surrounding the conductive connectors and the integrated circuit die; and attaching a heat spreader to the package substrate, the heat spreader adhered to the dummy semiconductor feature. ### Claim 5 A method comprising: placing a die stack on a front side of a device wafer; bonding a front side of a dummy wafer to the front side of the device wafer, the die stack disposed in a recess in the front side of the dummy wafer; thinning a back side of the dummy wafer until the recess is exposed, thereby forming an opening extending through the dummy wafer; forming a first adhesive in the opening, top surfaces of the first adhesive, the dummy wafer, and the die stack being level; forming conductive connectors on a back side of the device wafer; and singulating the device wafer and the dummy wafer simultaneously, the device wafer singulated to form an integrated circuit die, the die stack disposed on the integrated circuit die, the dummy wafer singulated to form a dummy semiconductor feature, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die. ### Claim 6 (depends on 5) The method of claim 5 further comprising: forming vias extending from the front side of the dummy wafer into the dummy wafer. ### Claim 7 (depends on 5) The method of claim 5 further comprising: bonding the integrated circuit die to a package substrate with the conductive connectors; forming an underfill between the package substrate and the integrated circuit die, the underfill surrounding the conductive connectors; dispensing a thermal interface material on the integrated circuit die and the dummy semiconductor feature; and attaching a heat spreader to the package substrate and the thermal interface material, the thermal interface material thermally coupling the heat spreader to the dummy semiconductor feature and the integrated circuit die. ### Claim 8 (depends on 7) The method of claim 7 further comprising: before the singulating the device wafer and the dummy wafer, forming dummy metallization on the dummy wafer, wherein after attaching the heat spreader to the package substrate, the dummy metallization thermally couples the thermal interface material to the dummy semiconductor feature and the integrated circuit die. ### Claim 9 (depends on 7) The method of claim 7 further comprising: before attaching the heat spreader to the package substrate, dispensing a second adhesive on the dummy semiconductor feature and the integrated circuit die; and forming dummy conductive features on the second adhesive, the thermal interface material being disposed on the second adhesive and surrounding the dummy conductive features. ### Claim 10 (depends on 5) The method of claim 5 further comprising: bonding the integrated circuit die to a package substrate with the conductive connectors; forming an underfill between the package substrate and the integrated circuit die, the underfill surrounding the conductive connectors; and attaching a support ring to the package substrate, the support ring surrounding the integrated circuit die and the underfill. ### Claim 11 A method comprising: placing a die stack on a front side of an integrated circuit die; forming a plurality of conductive connectors on a back side of the integrated circuit die; bonding a dummy wafer to the front side of the integrated circuit die, the dummy wafer having a first portion covering the die stack after the bonding; thinning the dummy wafer to remove the first portion of the dummy wafer, the die stack being exposed after the thinning; forming a first adhesive between the die stack and the dummy wafer; and singulating the dummy wafer to form a dummy semiconductor feature on the front side of the integrated circuit die, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature being electrically isolated from the die stack and the integrated circuit die. ### Claim 12 (depends on 11) The method of claim 11 further comprising: forming the integrated circuit die in a device wafer; and before bonding the dummy wafer to the front side of the integrated circuit die, singulating the integrated circuit die from the device wafer, wherein the dummy wafer is bonded to the singulated integrated circuit die. ### Claim 13 (depends on 11) The method of claim 11 further comprising: forming the integrated circuit die in a device wafer, wherein the dummy wafer is bonded to the device wafer, and wherein singulating the dummy wafer comprises simultaneously singulating the device wafer and the dummy wafer. ### Claim 14 (depends on 13) The method of claim 13 further comprising: before singulating the device wafer and the dummy wafer, plating dummy metallization on the dummy wafer and the integrated circuit die. ### Claim 15 (depends on 11) The method of claim 11, wherein bonding the dummy wafer to the front side of the integrated circuit die comprises forming fusion bonds between the dummy wafer and the integrated circuit die. ### Claim 16 (depends on 11) The method of claim 11, wherein bonding the dummy wafer to the front side of the integrated circuit die comprises forming hybrid bonds between the dummy wafer and the integrated circuit die. ### Claim 17 (depends on 11) The method of claim 11, wherein bonding the dummy wafer to the front side of the integrated circuit die comprises forming solder bonds between the dummy wafer and the integrated circuit die. ### Claim 18 (depends on 11) The method of claim 11, wherein forming the first adhesive between the die stack and the dummy wafer comprises: before the singulating the dummy wafer, thinning a back side of the dummy wafer until the die stack is exposed, thereby forming an opening extending through the dummy wafer; and dispensing the first adhesive in the opening; and planarizing the first adhesive and the dummy wafer such that top surfaces of the first adhesive, the dummy wafer, and the die stack are level. ### Claim 19 (depends on 11) The method of claim 11, wherein forming the first adhesive between the die stack and the dummy wafer comprises: before bonding the dummy wafer to the front side of the integrated circuit die, dispensing the first adhesive on the die stack; and placing the dummy wafer on the first adhesive. ### Claim 20 (depends on 11) The method of claim 11 further comprising: forming vias extending at least partially into the dummy wafer.