# US 10,483,182 B2 · Intermediate connector, semiconductor device including intermediate connector, and method of manufacturing intermediate connector

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- Number: US 10,483,182 B2
- Document ID: US10483182B2
- Status: Granted
- Kind: B2
- Application number: 16/091,155
- Filed: 2016-05-24
- Published: 2019-05-02
- Granted: 2019-11-19
- Earliest claimed: 2016-05-24
- Assignees: Noda Screen Co., Ltd.
- Applicants: Noda Screen Co., Ltd.
- Inventors: Seisei Oyamada
- Web page: https://patentgrep.com/patent/US10483182B2

## CPC

- H10W 78/00: Detachable holders for supporting packaged chips in operation
- H05K 1/02: Details
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 44/401: {Resistive arrangements (H10W44/20, H10W42/80 take precedence)}
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/072: {of bump connectors}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

An intermediate connector includes a power source bus bar as an elongated thin plate to be connected to each power source pad of a semiconductor integrated circuit, a ground bus bar as an elongated thin plate to be connected to each ground pad of the semiconductor integrated circuit, a thin film insulator layer formed between the power source bus bar and the ground bus bar, and a conductive path portion as an elongated thin plate including a plurality of conductive paths to be connected to each signal pad of the semiconductor integrated circuit. The power source bus bar, the ground bus bar, and the conductive path portion are arranged in parallel correspondingly to a parallel arrangement of a power source pad row, a ground pad row, and a signal pad row of the semiconductor integrated circuit.

## Claims

### Claim 1

An intermediate connector that is provided between a semiconductor integrated circuit and a circuit board on which the semiconductor integrated circuit is mounted, and electrically connects the semiconductor integrated circuit and the circuit board,
the semiconductor integrated circuit including a bump mounting face on which a power source pad row including a plurality of power source pads, a ground pad row including a plurality of ground pads, and a signal pad row including a plurality of signal pads are arranged in parallel,
the intermediate connector comprising:
a power source bus bar in a form of an elongated thin plate that has a length of at least a length of the power source pad row, and is to be connected to each of the power source pads of the power source pad row;
a ground bus bar in a form of an elongated thin plate that has a length of at least a length of the ground pad row, and is to be connected to each of the ground pads of the ground pad row;
a thin film insulator layer that is formed between the power source bus bar and the ground bus bar; and
a conductive path portion in a form of an elongated thin plate that has a length of at least a length of the signal pad row, and includes a plurality of conductive paths to be connected to each of the signal pads of the signal pad row,
wherein the power source bus bar, the ground bus bar, and the conductive path portion are joined together in a parallel arrangement corresponding to the parallel arrangement of the power source pad row, the ground pad row, and the signal pad row, each of which being in a standing state such that a longitudinal direction of the thin plate is parallel to the bump mounting face of the semiconductor integrated circuit.

### Claim 2 (depends on 1)

The intermediate connector according to claim 1, further comprising at least one of:
a damping resistor that is formed on a connection face to be connected to the semiconductor integrated circuit, that is an upper end face of the power source bus bar, at positions corresponding to the plurality of power source pads, and has a sheet resistance higher than a sheet resistance of the power source bus bar; and
a damping resistor that is formed on a connection face to be connected to the semiconductor integrated circuit, that is an upper end face of the ground bus bar, at positions corresponding to the plurality of ground pads, and has a sheet resistance higher than a sheet resistance of the ground bus bar.

### Claim 3 (depends on 1)

The intermediate connector according to claim 1, wherein the power source bus bar includes a plurality of types of power source bus bars having different power source voltages.

### Claim 4 (depends on 1)

A semiconductor device comprising:
a semiconductor integrated circuit including a pad face on which a power source pad row including a plurality of power source pads, a ground pad row including a plurality of ground pad rows, and a signal pad row including a plurality of signal pads are arranged in parallel; and
the intermediate connector according to claim 1.

### Claim 5

A method of manufacturing an intermediate connector that is provided between a semiconductor integrated circuit and a circuit board on which the semiconductor integrated circuit is mounted, and electrically connects the semiconductor integrated circuit and the circuit board,
the semiconductor integrated circuit including a bump mounting face on which a power source pad row including a plurality of power source pads, a ground pad row including a plurality of ground pad rows, and a signal pad row including a plurality of signal pads are arranged in parallel,
the method comprising:
a step of forming a power source bus bar in a form of an elongated thin plate that has a length of at least a length of the power source pad row, and to be connected to each of the power source pads of the power source pad row;
a step of forming a ground bus bar in a form of an elongated thin plate that has a length of at least a length of the ground pad row, and is to be connected to each of the ground pads of the ground pad row;
a step of forming an insulator layer between the power source bus bar and the ground bus bar;
a step of forming a conductive path portion in a form of an elongated thin plate that has a length of at least a length of the signal pad row, and includes a plurality of conductive paths to be connected to each of the signal pads of the signal pad row; and
a joining step of joining the power source bus bar, the ground bus bar, and the conductive path portion together in a parallel arrangement corresponding to the parallel arrangement of the power source pad row, the ground pad row, and the signal pad row, each of which being in a standing state such that a longitudinal direction of the thin plate is parallel to the bump mounting face of the semiconductor integrated circuit.

### Claim 6 (depends on 5)

The method of manufacturing an intermediate connector according to claim 5, wherein the joining step further includes:
a primary intermediate forming step of forming a primary intermediate for the intermediate connector that is a laminate of units, by joining the power source bus bars, the ground bus bars, and the conductive path portions that have been joined as the units;
a secondary intermediate forming step of forming a plurality of secondary intermediates for the intermediate connector, by cutting the primary intermediate into a strip form corresponding to a size of the semiconductor integrated circuit; and
a connector forming step of forming the intermediate connector by joining the plurality of secondary intermediates.