# US 10,483,174 B1 · Integrated circuit component and package structure having the same

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- Number: US 10,483,174 B1
- Document ID: US10483174B1
- Status: Granted
- Kind: B1
- Application number: 16/016,662
- Filed: 2018-06-25
- Granted: 2019-11-19
- Earliest claimed: 2018-06-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Tzuan-Horng Liu; Chao-Hsiang Yang; Hsien-Wei Chen; Ming-Fa Chen
- Web page: https://patentgrep.com/patent/US10483174B1

## CPC

- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 74/014: {using batch processing}
- H10W 70/095: {of vias therein}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01204: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/01233: {in liquid form, e.g. spin coating, spray coating or immersion coating}
- H10W 72/01235: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01255: {by using masks}
- H10W 72/01257: {by reflowing}
- H10W 72/019: {of bond pads}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/01938: {in gaseous form, e.g. by CVD or PVD}
- H10W 72/01953: {by etching}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07252: {changes in structures or sizes}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07354: {changes in dispositions}
- H10W 72/221: {Structures or relative sizes}
- H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core}
- H10W 72/228: {Multiple bumps having different structures}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/354: {comprising polymers}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 72/985: {Alignment aids, e.g. alignment marks}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure includes a semiconductor substrate, conductive pads, and conductive vias. The conductive pads are located on and electrically connected to the semiconductor substrate, and each have a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region. The conductive vias are respectively located on the core contact regions of the conductive pads.

## Claims

### Claim 1

An integrated circuit component, comprising:
a semiconductor substrate;
conductive pads, located on and electrically connected to the semiconductor substrate and each having a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region; and
conductive vias, respectively located on the core contact regions of the conductive pads.

### Claim 2 (depends on 1)

The integrated circuit component of claim 1, further comprising:
a passivation layer, located on the semiconductor substrate, wherein the passivation layer partially covers the conductive pads.

### Claim 3 (depends on 2)

The integrated circuit component of claim 2, wherein the testing regions and the core contact regions of the conductive pads are respectively exposed by first openings formed in the passivation layer.

### Claim 4 (depends on 2)

The integrated circuit component of claim 2, further comprising:
a post-passivation layer, located on the semiconductor substrate, wherein the testing regions of the conductive pads are covered by the post-passivation layer, and the core contact regions of the conductive pads are respectively exposed by second openings formed in the post-passivation layer.

### Claim 5 (depends on 4)

The integrated circuit component of claim 4, wherein each of the conductive vias is physically connected to a respective one of the core contact regions of the conductive pads through a respective one of the second openings formed in the post-passivation layer and a respective one of the first openings of the passivation layer.

### Claim 6 (depends on 1)

The integrated circuit component of claim 1, wherein the testing region of at least one of the conductive pads has a probe mark.

### Claim 7 (depends on 6)

The integrated circuit component of claim 6, wherein a surface of the testing region of the at least one of the conductive pads having the probe mark comprises a non-planar surface.

### Claim 8 (depends on 6)

The integrated circuit component of claim 6, wherein a surface roughness of the surface of the testing region of the at least one of the conductive pads having the probe mark is greater than a surface roughness of a surface of the core contact region of the at least one of the conductive pads.

### Claim 9 (depends on 1)

The integrated circuit component of claim 1, wherein each of the conductive pads further comprises an alignment mark, wherein the alignment mark is aligned with an edge of the testing region immediately adjacent to the core contact region.

### Claim 10

A package structure, comprising:
a carrier substrate;
an integrated circuit component, located on the carrier substrate, wherein the integrated circuit component comprises:
a semiconductor substrate;
conductive pads, located on and electrically connected to the semiconductor substrate and each having a testing region and a contact region comprising a core contact region and a buffer contact region, wherein along one direction, the conductive pads each have a maximum length less than a sum of a maximum length of the testing region and a maximum length of the buffer contact region; and
conductive vias, respectively located on the core contact regions of the conductive pads, wherein the integrated circuit component is electrically connected to the carrier substrate through the conductive vias; and
an underfill, encapsulating sidewalls of the conductive vias.

### Claim 11 (depends on 10)

The package structure of claim 10, wherein the testing region of at least one of the conductive pads has a probe mark.

### Claim 12 (depends on 10)

The package structure of claim 10, wherein in each of the conductive pads, an edge of the core contact region is in contact with an edge of the testing region.

### Claim 13 (depends on 10)

The package structure of claim 10, wherein each of the conductive pads further comprises an alignment mark, wherein the alignment mark is aligned with an edge of the testing region immediately adjacent to the core contact region.