# US 10,483,171 B2 · Method and apparatus with channel stop doped devices

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- Number: US 10,483,171 B2
- Document ID: US10483171B2
- Status: Granted
- Kind: B2
- Application number: 15/918,236
- Filed: 2018-03-12
- Published: 2018-08-09
- Granted: 2019-11-19
- Earliest claimed: 2012-12-04
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Victor Moroz
- Web page: https://patentgrep.com/patent/US10483171B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10W 10/0125: {comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- H10D 84/0193: {the components including FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and apparatuses relate to implanting a surface of a semiconductor substrate with dopants, making undoped semiconductor material directly on the surface implanted with the dopants, and making a transistor with a transistor channel in the undoped semiconductor material, such that the transistor channel of the transistor remains undoped throughout manufacture of the integrated circuit.

## Claims

### Claim 1

A method of performing channel stop doping in an integrated circuit, comprising:
implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
making epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxial semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxial semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface; and
making a transistor with a transistor channel in the epitaxial semiconductor material, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 2 (depends on 1)

The method of claim 1, wherein the implanted dopants provide latchup protection of the transistor against other structures.

### Claim 3 (depends on 1)

The method of claim 1, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.

### Claim 4

A nontransitory computer readable medium with computer executable instructions determining a layout of an integrated circuit design, the computer executable instructions including:
first computer executable instructions defining first layout locations for implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants; and
second computer executable instructions defining second layout locations for making a transistor with a transistor channel in epitaxial semiconductor material, the epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxial semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxial semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 5 (depends on 4)

The medium of claim 4, wherein the implanted dopants provide latchup protection of the transistor against other structures.

### Claim 6 (depends on 4)

The medium of claim 4, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.

### Claim 7 (depends on 4)

The medium of claim 4, wherein the computer executable instructions include:
third computer executable instructions defining third layout locations for making the epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface with the p-type dopants.

### Claim 8

A set of lithographic masks determining a layout of an integrated circuit design,
including:
a first lithographic mask defining first layout locations for implanting a first part of a surface of a semiconductor substrate with dopants and a second part of the surface with p-type dopants, resulting in a junction between the first and second parts having implants impinging from one of the first and second parts to another of the first and second parts; and
a second lithographic mask defining second layout locations for making a transistor with a transistor channel in epitaxial semiconductor material, the epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxial semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxial semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 9 (depends on 8)

The masks of claim 8, wherein the implanted dopants provide latchup protection of the transistor against other structures.

### Claim 10 (depends on 8)

The masks of claim 8, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.

### Claim 11 (depends on 8)

The masks of claim 8, wherein the set of lithographic masks include:
a third lithographic mask defining third layout locations for making the epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface with the p-type dopants.

### Claim 12

A computer system for laying out an integrated circuit design, the computer system comprising a processor and a memory,
the computer system generating a layout of the integrated circuit design, the layout defining a plurality of masks, the computer system configured to perform computer executable instructions comprising:
first computer executable instructions defining first layout locations for implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants; and
second computer executable instructions defining second layout locations making a transistor with a transistor channel in epitaxial semiconductor material, the epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxial semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxial semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 13 (depends on 12)

The system of claim 12, wherein the implanted dopants provide latchup protection of the transistor against other structures.

### Claim 14 (depends on 12)

The system of claim 12, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.

### Claim 15 (depends on 12)

The system of claim 12, wherein the computer executable instructions include:
third computer executable instructions defining third layout locations for making the epitaxial semiconductor material directly on the first part of the surface implanted with the n-type dopants and on the second part of the surface with the p-type dopants.

### Claim 16

A method of performing channel stop doping in an integrated circuit, comprising:
implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
epitaxially growing essentially undoped semiconductor material directly on the entire substrate surface, including both on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxially grown essentially undoped semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxially grown essentially undoped semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface;
forming isolation trenches through the epitaxially grown undoped semiconductor material directly on the entire substrate surface and between the first part of the surface implanted with the n-type dopants and the second part of the surface implanted with the p-type dopants; and
making a transistor with a transistor channel in the epitaxial semiconductor material, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 17 (depends on 16)

The method of claim 16, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.

### Claim 18

A nontransitory computer readable medium with computer executable instructions determining a layout of an integrated circuit design, the computer executable instructions including:
first computer executable instructions defining first layout locations for implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
second computer executable instructions defining second layout locations for epitaxially growing essentially undoped semiconductor material directly on the entire substrate surface, including both on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxially grown essentially undoped semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxially grown essentially undoped semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface;
third computer executable instructions defining third layout locations for forming isolation trenches through the epitaxially grown undoped semiconductor material directly on the entire substrate surface and between the first part of the surface implanted with the n-type dopants and the second part of the surface implanted with the p-type dopants; and
fourth computer executable instructions defining fourth layout locations for making a transistor with a transistor channel in the epitaxial semiconductor material, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 19 (depends on 18)

The nontransitory computer readable medium of claim 18, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.

### Claim 20

A set of lithographic masks determining a layout of an integrated circuit design, including:
a first lithographic mask defining first layout locations for implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
a second lithographic mask defining second layout locations for epitaxially growing essentially undoped semiconductor material directly on the entire substrate surface, including both on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxially grown essentially undoped semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxially grown essentially undoped semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface;
a third lithographic mask defining third layout locations for forming isolation trenches through the epitaxially grown undoped semiconductor material directly on the entire substrate surface and between the first part of the surface implanted with the n-type dopants and the second part of the surface implanted with the p-type dopants; and
a fourth lithographic mask defining fourth layout locations for making a transistor with a transistor channel in the epitaxial semiconductor material, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 21 (depends on 20)

The set of lithographic masks of claim 20, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.

### Claim 22

A computer system for laying out an integrated circuit design, the computer system comprising a processor and a memory,
the computer system generating a layout of the integrated circuit design, the layout defining a plurality of masks, the computer system configured to perform computer executable instructions comprising:
first computer executable instructions defining first layout locations for implanting a first part of a surface of a semiconductor substrate with n-type dopants and a second part of the surface with p-type dopants;
second computer executable instructions defining second layout locations for epitaxially growing essentially undoped semiconductor material directly on the entire substrate surface, including both on the first part of the surface implanted with the n-type dopants and on the second part of the surface implanted with the p-type dopants, the epitaxially grown essentially undoped semiconductor material having a dopant concentration on the first part of the surface and on the second part of the surface, the dopant concentration changing by a decade over a depth of less than 3 nanometers at an interface between the epitaxially grown essentially undoped semiconductor material and the semiconductor substrate under process conditions including temperature developed to cause the dopant concentration changing at the interface;
third computer executable instructions defining third layout locations for forming isolation trenches through the epitaxially grown undoped semiconductor material directly on the entire substrate surface and between the first part of the surface implanted with the n-type dopants and the second part of the surface implanted with the p-type dopants; and
fourth computer executable instructions defining fourth layout locations for making a transistor with a transistor channel in the epitaxial semiconductor material, such that the transistor channel, in the epitaxial semiconductor material, of the transistor remains essentially undoped throughout manufacture of the integrated circuit.

### Claim 23 (depends on 22)

The computer system of claim 22, wherein the transistor is one of a plurality of transistors with the transistor channel in the epitaxial semiconductor material, and the transistor channels of the plurality of transistors all remain essentially undoped throughout manufacture of the integrated circuit.