# US 10,483,166 B1 · Vertically stacked transistors

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- Number: US 10,483,166 B1
- Document ID: US10483166B1
- Status: Granted
- Kind: B1
- Application number: 16/018,710
- Filed: 2018-06-26
- Granted: 2019-11-19
- Earliest claimed: 2018-06-26
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Tenko Yamahita; Chun Wing Yeung; Chen Zhang
- Web page: https://patentgrep.com/patent/US10483166B1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/00: Three-dimensional [3D] integrated devices
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/364: {of IGFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/01: {Manufacture or treatment}
- H10W 20/42: Vias, e.g. via plugs
- H10D 62/121: {oriented parallel to substrates}
- H10P 50/242: {of Group IV materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a vertically stacked nanosheet semiconductor device includes epitaxially growing at least three layers each of alternating silicon and silicon germanium layers on a substrate and patterning a gate structure. The method includes performing at least three reactive ion etch processes forming recesses. The method includes forming source or drain regions in a channel formed by a shallow trench isolation layer formed in the recesses. The method includes growing a first epitaxial layer on the source or drain regions, forming at least three pFET structures. The method includes etching away a portion of each of the pFET structures and depositing a dielectric layer on each. The method includes growing a second epitaxial layer, forming at least three nFET structures. Each layer of the pFET structure and nFET structure are stacked vertically and each layer of the pFET structure and nFET structures have independent source or drain contacts.

## Claims

### Claim 1

A method of fabricating a vertically stacked nanosheet semiconductor device, the method comprising:
forming a nanosheet stack by epitaxially growing alternating layers of a first material and a second material on a substrate and patterning a gate structure on the nanosheet stacks;
performing a first reactive ion etch on the nanosheet stack forming recesses on the substrate;
performing a second reactive ion etch on the alternating layers of the first material and the second material;
depositing inner spacers and a shallow trench isolation layer in the recesses;
forming source or drain (S/D) regions in a channel formed by the shallow trench isolation layer;
growing a first epitaxial layer on the source or drain regions, forming a first pFET structure and a second pFET structure;
etching away a portion of the first pFET structure and the second pFET structure and depositing a dielectric layer on the first pFET structure and the second pFET structure; and
growing a second epitaxial layer on the source or drain regions, forming a first nFET structure and a second nFET structure;
wherein at least one of the first pFET structure and the first nFET structure or the second pFET structure and the second nFET structure have individual contacts, wherein the individual contacts enable independent voltage control across the semiconductor device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising depositing a hardmask layer on a top layer of the nanosheet stack before the first reactive ion etching.

### Claim 3 (depends on 1)

The method of claim 1, wherein at least one of the first pFET structure and the first nFET structure or the second pFET structure and the second nFET structure share a source or drain contact.

### Claim 4 (depends on 3)

The method of claim 3, wherein a merge contact shape differs from individual contact shapes.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first and second pFET structure and the first and second nFET structure share a common gate.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first pFET structure and the first nFET structure are disposed vertically to one another.

### Claim 7

The method of claim pFET structure nFET structure 1, wherein the first material comprises silicon and the second material comprises silicon germanium.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second pFET structure and the second nFET structure are disposed vertically to one another.

### Claim 9 (depends on 1)

The method of claim 1, wherein the first epitaxial layer comprises silicon germanium.

### Claim 10 (depends on 1)

The method of claim 1, wherein the second epitaxial layer comprises silicon epitaxy.

### Claim 11

A method of fabricating a vertically stacked nanosheet semiconductor device, the method comprising:
epitaxially growing at least three layers each of alternating silicon and silicon germanium layers on a substrate, forming a nanosheet stack and patterning a gate structure on the nanosheet stacks;
performing at least three reactive ion etch processes on the nanosheet stack, forming recesses on the substrate;
forming source or drain regions in a channel formed by a shallow trench isolation layer formed in the recesses;
growing a first epitaxial layer on the source or drain regions, and repeating the process at least two times to form at least three pFET structures;
etching away a portion of each of the pFET structures and depositing a dielectric layer on the each pFET structure; and
growing a second epitaxial layer on the source or drain regions, and repeating the process at least two times to form at least three nFET structures;
wherein each layer of the pFET structure and nFET structure are stacked vertically and wherein each layer of the pFET structure and nFET structures have independent source or drain contacts.

### Claim 12 (depends on 11)

The method of claim 11, wherein each pFET structure and nFET structure has the same effective channel width.

### Claim 13 (depends on 11)

The method of claim 11, wherein each pFET structure and nFET structure has the same effective drive current.

### Claim 14 (depends on 11)

The method of claim 11, wherein the first epitaxial layer comprises silicon germanium.

### Claim 15 (depends on 11)

The method of claim 11, wherein the second epitaxial layer comprises silicon epitaxy.

### Claim 16 (depends on 11)

The method of claim 11, wherein an area of the nanosheet semiconductor device is reduced by at least 40% as compared to a semiconductor device as compared to a semiconductor device without vertical stacking of the pFET structure and nFET structure.