# US 10,483,164 B2 · Semiconductor structure and method for manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,164 B2 - Document ID: US10483164B2 - Status: Granted - Kind: B2 - Application number: 15/881,159 - Filed: 2018-01-26 - Published: 2019-05-16 - Granted: 2019-11-19 - Earliest claimed: 2017-11-14 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Ltd. - Inventors: Yan-Ming Tsai; Wei-Yip Loh; Yu-Ming Huang; Hung-Hsu Chen; Chih-Wei Chang - Web page: https://patentgrep.com/patent/US10483164B2 ## CPC - H10W 20/066: {by forming silicides of refractory metals} - H10D 30/0212: {using self-aligned silicidation} - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 64/0112: {using conductive layers comprising silicides} - H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10W 20/0698: {Local interconnections} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/083: {the openings being via holes penetrating underlying conductors} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A method for manufacturing a semiconductor includes following steps. An epitaxial structure including a first semiconductor material and a second semiconductor material is provided. A lattice constant of the second semiconductor material is greater than a lattice constant of the first semiconductor material. A metal-containing layer is deposited on the epitaxial structure. The metal containing layer includes a first metal material and a second metal material. An atomic size of the second metal material is greater than an atomic size of the first metal material. The metal-containing layer and the epitaxial structure are annealed to form a metal silicide layer on the epitaxial structure. The metal silicide layer includes the first semiconductor material, the second semiconductor material, the first metal material, and the second metal material. ## Claims ### Claim 1 A method for manufacturing a semiconductor structure, comprising: providing an epitaxial structure comprising a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material being greater than a lattice constant of the first semiconductor material; depositing a metal-containing layer on the epitaxial structure, the metal-containing layer comprising the first semiconductor material, a first metal material and a second metal material, and an atomic size of the second metal material being greater than an atomic size of the first metal material; and annealing the metal-containing layer and the epitaxial structure to form a metal silicide layer on the epitaxial structure, the metal silicide layer comprising the first semiconductor material, the second semiconductor material, the first metal material and the second metal material. ### Claim 2 (depends on 1) The method of claim 1, wherein the first semiconductor material comprises silicon (Si), and the second semiconductor material comprises germanium (Ge). ### Claim 3 (depends on 1) The method of claim 1, wherein a concentration of the second metal material in the metal-containing layer is less than a concentration of the first metal material in the metal-containing layer. ### Claim 4 (depends on 1) The method of claim 1, wherein the first metal material comprises titanium (Ti). ### Claim 5 (depends on 4) The method of claim 4, wherein the second metal material comprises tungsten (W), tantalum (Ta), platinum (Pt), niobium (Nb), or gold (Au). ### Claim 6 (depends on 1) The method of claim 1, wherein a temperature of the anneal is lower than 600° C. ### Claim 7 (depends on 1) The method of claim 1, further comprising forming a contact plug over the epitaxial structure. ### Claim 8 A method for forming a semiconductor structure, comprising: providing an epitaxial structure comprising a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material being greater than a lattice constant of the first semiconductor material; disposing a metal-containing layer on the epitaxial structure, the metal-containing layer comprising at least a first metal material; performing an ion implantation to implant ions of a second metal material to the metal-containing layer; and annealing the metal-containing layer and the epitaxial structure to form a metal silicide layer on the epitaxial structure, the metal silicide layer comprising the first semiconductor material, the second semiconductor material, the first metal material and the second metal material. ### Claim 9 (depends on 8) The method of claim 8, wherein the first semiconductor material comprises Si, and the second semiconductor material comprises Ge. ### Claim 10 (depends on 8) The method of claim 8, wherein the metal-containing layer further comprises the first semiconductor material. ### Claim 11 (depends on 8) The method of claim 8, wherein an atomic size of the second metal material is greater than an atomic size of the first metal material. ### Claim 12 (depends on 8) The method of claim 8, wherein a concentration of the second metal material in the metal silicide layer is less than a concentration of the first metal material in the metal silicide layer. ### Claim 13 (depends on 8) The method of claim 8, wherein the first metal material comprises Ti. ### Claim 14 (depends on 13) The method of claim 13, wherein the second metal material comprises W, Ta, Pt, Nb, or Au. ### Claim 15 (depends on 8) The method of claim 8, wherein a temperature of the anneal is lower than 600° C. ### Claim 16 A semiconductor structure comprising: an epitaxial structure comprising a first semiconductor material and a second semiconductor material, and a lattice constant of the second semiconductor material being greater than a lattice constant of the first semiconductor material; a quaternary metal silicide layer on the epitaxial structure, wherein the quaternary silicide layer comprises the first semiconductor material, the second semiconductor material, a first metal material and a second metal material, and an atomic size of the second metal material is greater than an atomic size of the first metal material; and a conductive plug penetrating the quaternary metal silicide layer, wherein a bottom most surface of the conductive plug is lower than a bottom most surface of the quaternary silicide layer. ### Claim 17 (depends on 16) The semiconductor structure of claim 16, wherein the quaternary metal silicide layer comprises TiXSiGe. ### Claim 18 (depends on 17) The semiconductor structure of claim 17, wherein “X” of the quaternary metal silicide layer comprises W, Ta, Pt, Nb, or Au. ### Claim 19 (depends on 16) The semiconductor structure of claim 16, wherein a concentration of the second metal material is less than a concentration of the first metal material. ### Claim 20 (depends on 8) The method of claim 8, further comprising forming a contact plug over the epitaxial structure.