# US 10,483,163 B2 · Self-forming barrier process

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- Number: US 10,483,163 B2
- Document ID: US10483163B2
- Status: Granted
- Kind: B2
- Application number: 16/216,346
- Filed: 2018-12-11
- Published: 2019-04-25
- Granted: 2019-11-19
- Earliest claimed: 2017-06-27
- Assignees: Lam Research Corporation
- Applicants: Lam Research Corporation
- Inventors: Aniruddha Joi; Yezdi Dordi
- Web page: https://patentgrep.com/patent/US10483163B2

## CPC

- H10W 20/049: {by diffusing alloying elements}
- C23C 18/1651: {Two or more layers only obtained by electroless plating}
- C23C 18/1692: {Heat-treatment}
- C23C 18/48: Coating with alloys
- C23C 18/50: with alloys based on iron, cobalt or nickel
- C25D 3/58: containing more than 50% by weight of copper
- C25D 5/50: by heat-treatment
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10W 20/033: {in openings in dielectrics}
- H10W 20/036: {the barrier, adhesion or liner layers being within a main fill metal}
- H10W 20/055: {by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition}
- H10W 20/0552: {by diffusing metallic dopants to react with dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/4403: {based on metals, e.g. alloys, metal silicides (H10W20/4484 takes precedence)}
- H10W 20/4437: {the principal metal being a transition metal}
- C23C 18/54: Contact plating, i.e. electroless electrochemical plating
- H10W 20/076: {in via holes or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method is provided, including the following operations: performing a deposition process on a substrate, the deposition process configured to deposit a ruthenium layer in a feature on the substrate, the ruthenium layer being doped with zinc at an atomic percentage less than approximately 30 percent; after depositing the ruthenium layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the ruthenium layer and an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the ruthenium layer.

## Claims

### Claim 1

A method, comprising:
performing a deposition process on a substrate, the deposition process configured to deposit a ruthenium layer in a feature on the substrate, the ruthenium layer being doped with zinc at an atomic percentage less than approximately 30 percent;
after depositing the ruthenium layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface at an oxide layer of the substrate, the migration of the zinc producing an adhesive barrier at the interface that inhibits electromigration of the ruthenium layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the feature does not include a barrier layer prior to the deposition of the ruthenium layer.

### Claim 3 (depends on 1)

The method of claim 1, wherein the annealing of the substrate causes bonding of the zinc to oxygen at the interface to form the barrier.

### Claim 4 (depends on 1)

The method of claim 1, wherein the annealing of the substrate is performed at a temperature less than approximately 350 degrees Celsius.

### Claim 5 (depends on 1)

The method of claim 1, wherein the deposition process is defined by an electroless deposition process configured to co-deposit ruthenium and zinc.

### Claim 6 (depends on 1)

The method of claim 1, wherein the feature is a via, and wherein the method defines a pre-fill operation configured to partially fill the via with the ruthenium layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the interface is defined along a sidewall of the via.

### Claim 8

A method, comprising:
performing a deposition process on a substrate, the deposition process configured to deposit a metallic layer in a feature on the substrate, the metallic layer consisting of ruthenium doped with zinc at an atomic percentage less than approximately 5 percent;
after depositing the metallic layer, annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface of the metallic layer and an oxide layer of the substrate, the migration of the zinc producing a barrier at the interface that inhibits electromigration of the metallic layer.

### Claim 9 (depends on 8)

The method of claim 8, wherein the feature does not include a barrier layer prior to the deposition of the metallic layer.

### Claim 10 (depends on 8)

The method of claim 8, wherein the annealing of the substrate causes bonding of the zinc to oxygen at the interface to form the barrier.

### Claim 11 (depends on 8)

The method of claim 8, wherein the annealing of the substrate is performed at a temperature less than approximately 350 degrees Celsius.

### Claim 12 (depends on 8)

The method of claim 8, wherein the deposition process is defined by an electroless deposition process.

### Claim 13 (depends on 8)

The method of claim 8, wherein the feature is a via, and wherein the method defines a pre-fill operation configured to partially fill the via with the metallic layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the interface of the metallic layer and the oxide layer is defined along a sidewall of the via.

### Claim 15

A method, comprising:
performing a first deposition process on a substrate, the first deposition process configured to deposit a ruthenium layer in a feature on the substrate;
performing a second deposition process on the substrate, the second deposition process configured to deposit a conformal layer of zinc over the ruthenium layer;
annealing the substrate, wherein the annealing is configured to cause migration of the zinc to an interface at an oxide layer of the substrate, the migration of the zinc producing a barrier at the interface that inhibits electromigration of the ruthenium layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the feature does not include a barrier layer prior to the deposition of the ruthenium layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the annealing of the substrate causes bonding of the zinc to oxygen at the interface to form the barrier.

### Claim 18 (depends on 15)

The method of claim 15, wherein the annealing of the substrate is performed at a temperature less than approximately 350 degrees Celsius.

### Claim 19 (depends on 15)

The method of claim 15, wherein the first deposition process is defined by an electroless deposition process configured to deposit ruthenium.

### Claim 20 (depends on 15)

The method of claim 15, wherein the feature is a via, and wherein the method defines a pre-fill operation configured to partially fill the via with the ruthenium layer.

### Claim 21 (depends on 20)

The method of claim 20, wherein the interface is defined along a sidewall of the via.