# US 10,483,162 B2 · Semiconductor structure of interconnect and fabrication method thereof

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- Number: US 10,483,162 B2
- Document ID: US10483162B2
- Status: Granted
- Kind: B2
- Application number: 15/936,766
- Filed: 2018-03-27
- Published: 2018-10-04
- Granted: 2019-11-19
- Earliest claimed: 2017-03-29
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Hao Deng
- Web page: https://patentgrep.com/patent/US10483162B2

## CPC

- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- C23C 14/0641: {Nitrides (C23C14/0617 takes precedence)}
- C23C 16/045: {Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates}
- C23C 16/34: Nitrides {(C23C16/303 takes precedence)}
- C23C 16/45531: {specially adapted for making ternary or higher compositions}
- C23F 17/00: Multi-step processes for surface treatment of metallic material involving at least one process provided for in class C23 and at least one process covered by subclass C21D or C22F or class C25 (coating for obtaining at least two superposed coatings either by methods not provided for in a single one of main groups C23C2/00 - C23C26/00, or by combinations of methods providedfor in subclasses C23C and C25D, C23C28/00)
- C25D 7/123: {Semiconductors first coated with a seed layer or a conductive layer}
- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10P 14/432: {using selective deposition}
- H10P 14/44: Physical vapour deposition [PVD]
- H10P 14/47: Electrolytic deposition, i.e. electroplating; Electroless plating
- H10W 20/033: {in openings in dielectrics}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- C25D 3/38: of copper
- H10W 20/48: Insulating materials thereof
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- C23F: NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE (working metal by laser beams B23K26/00; desurfacing by applying flames B23K7/00; working of metal by electro-erosion B23H; producing decorative effects by removing surface material, e.g. by engraving, by etching, B44C1/22; electrolytic etching or polishing C25F); INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C25D: PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a fabrication method are provided. The fabrication method includes: providing a substrate; forming a dielectric layer with an opening on the substrate; forming a first barrier layer on sidewall and bottom surfaces of the opening, the first barrier layer being doped by manganese; and forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a dielectric layer with an opening on the substrate;
forming a first barrier layer on sidewall and bottom surfaces of the opening, wherein the first barrier layer is made of a material including tantalum nitride doped with manganese, the first barrier layer is formed by an atomic layer deposition process, and forming the first barrier layer comprises:
introducing a tantalum source gas to the substrate, a portion of the tantalum source gas being adsorbed on the substrate;
evacuating the tantalum source gas that is not adsorbed on the substrate;
introducing a manganese source gas to the substrate, a portion of the manganese source gas being adsorbed on the substrate;
evacuating the manganese source gas that is not adsorbed on the substrate;
introducing a nitrogen source gas to the substrate, a portion of the nitrogen source gas being adsorbed on the substrate; and
evacuating the nitrogen source gas that is not adsorbed on the substrate, wherein the atomic layer deposition process uses:
the tantalum source gas including C10H30N5Ta, with a flow rate in a range of approximately 500 standard ml/min˜1500 standard ml/min;
the manganese source gas including (C5H5)2Mn, with a flow rate in a range of approximately 50 standard ml/min˜150 standard ml/min;
the nitrogen source gas including ammonia gas, with a flow rate in a range of approximately 500 standard ml/min˜2000 standard ml min;
a deposition temperature in a range of approximately 250° C.˜350° C.; and
a pressure in a reaction chamber in a range of approximately 2 Torr˜10 Torr; and
forming a metal interconnect on the first barrier layer, the metal interconnect being located within the opening.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
a thickness of the first barrier layer is in a range of approximately 15 Å to 50 Å.

### Claim 3 (depends on 1)

The method according to claim 1, wherein:
an atomic percentage concentration of manganese in the first barrier layer is in a range of 0.5% to 3%.

### Claim 4 (depends on 1)

The method according to claim 1, wherein:
the dielectric layer includes a single-layer structure; and
the dielectric layer is made of a low-K dielectric material having a dielectric constant value of less than about 3.9.

### Claim 5 (depends on 4)

The method according to claim 4, wherein:
the dielectric layer is made of one or more of SiCOH, boron-doped silicon dioxide, phosphorus-doped silicon dioxide, and boron phosphorus-doped silicon dioxide.

### Claim 6 (depends on 1)

The method according to claim 1, wherein forming the metal interconnect comprises:
forming a metal layer on the first barrier layer; and
planarizing the metal layer until a top surface of the dielectric layer is exposed, the planarized metal layer forming the metal interconnect.

### Claim 7 (depends on 6)

The method according to claim 6, wherein:
the metal layer is formed by an electroplating method.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
the metal interconnect is made of a material including copper.

### Claim 9 (depends on 1)

The method according to claim 1, wherein:
forming a second barrier layer on a top surface of the first barrier layer is after forming the first barrier layer and before forming the metal interconnect.

### Claim 10 (depends on 9)

The method according to claim 9, wherein:
the second barrier layer is made of a material including tantalum.

### Claim 11 (depends on 9)

The method according to claim 9, wherein:
the second barrier layer is formed by a physical vapor deposition process.

### Claim 12 (depends on 9)

The method according to claim 9, wherein:
a thickness of the second barrier layer is in a range of approximately 20 Å to 60 Å.

### Claim 13 (depends on 1)

The method according to claim 1, wherein:
the second barrier layer is formed directly on the first barrier layer and is not doped with manganese.

### Claim 14

A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a dielectric layer with an opening on the substrate;
forming a first barrier layer on sidewall and bottom surfaces of the opening, the first barrier layer being doped with manganese;
forming a second barrier layer on a top surface of the first barrier layer after forming the first barrier layer and before forming a metal interconnect; and
forming the metal interconnect on the first barrier layer, the metal interconnect being located within the opening, wherein the second barrier layer is formed by a physical vapor deposition process and the physical vapor deposition process uses:
a DC power in a range of approximately 5,000 W to 15,000 W;
an AC bias power in a range of approximately 200 W to 600 W;
a flow rate of argon in a range of approximately 5 standard ml/min˜30 standard ml/min; and
a pressure in a range of approximately 15 mTor˜60 mTorr.

### Claim 15 (depends on 14)

The method according to claim 14, wherein:
the first barrier layer is made of a material including tantalum nitride doped with manganese.

### Claim 16 (depends on 15)

The method according to claim 15, wherein:
the first barrier layer is formed by an atomic layer deposition process, and
forming the first barrier layer comprises:
introducing a tantalum source gas to the substrate, a portion of the tantalum source gas being adsorbed on the substrate;
evacuating the tantalum source gas that is not adsorbed on the substrate;
introducing a manganese source gas to the substrate, a portion of the manganese source gas being adsorbed on the substrate;
evacuating the manganese source gas that is not adsorbed on the substrate;
introducing a nitrogen source gas to the substrate, a portion of the nitrogen source gas being adsorbed on the substrate; and
evacuating the nitrogen source gas that is not adsorbed on the substrate.

### Claim 17 (depends on 16)

The method according to claim 16, wherein the atomic layer deposition process uses:
the tantalum source gas including C10H30N5Ta, with a flow rate in a range of approximately 500 standard ml/min˜1500 standard ml/min;
the manganese source gas including (C5H5)2Mn, with a flow rate in a range of approximately 50 standard ml/min˜150 standard ml/min;
the nitrogen source gas including ammonia gas, with a flow rate in a range of approximately 500 standard ml/min˜2000 standard ml min;
a deposition temperature in a range of approximately 250° C.˜350° C.; and
a pressure in a reaction chamber in a range of approximately 2 Torr˜10 Torr.

### Claim 18 (depends on 14)

The method according to claim 14, wherein:
a thickness of the first barrier layer is in a range of approximately 15 Λ to 50 Å.