# US 10,483,160 B2 · Ultra thin helmet dielectric layer for maskless air gap and replacement ILD processes

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- Number: US 10,483,160 B2
- Document ID: US10483160B2
- Status: Granted
- Kind: B2
- Application number: 15/745,235
- Filed: 2015-09-23
- Published: 2018-08-09
- Granted: 2019-11-19
- Earliest claimed: 2015-09-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jeffery D. Bielefeld; Manish Chandhok; Asad Iqbal; John D. Brooks
- Web page: https://patentgrep.com/patent/US10483160B2

## CPC

- H10W 20/46: comprising air gaps
- H10W 10/021: {of air gaps}
- H10W 10/20: Air gaps
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/096: {by contacting with gases, liquids or plasmas}
- H10W 20/097: {by thermally treating}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6905: {being a silicon carbide or silicon carbonitride and not containing oxygen, e.g. SiC or SiC:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A helmet layer is deposited on a plurality of conductive features on a first dielectric layer on a substrate. A second dielectric layer is deposited on a first portion of the helmet layer. An etch stop layer is deposited on a second portion the helmet layer.

## Claims

### Claim 1

A method to manufacture an electronic device, comprising:
depositing a helmet layer on a plurality of conductive features on a first dielectric layer on a substrate;
depositing a second dielectric layer on a first portion of the helmet layer; and
depositing an etch stop layer on a second portion of the helmet layer, wherein the etch stop layer comprises a dielectric material.

### Claim 2 (depends on 1)

The method of claim 1, further comprising forming a trench in the first dielectric layer between at least two of the conductive features, wherein the helmet layer is deposited on the trench and on a top portion and opposing sidewalls of the at least two of the conductive features.

### Claim 3 (depends on 1)

The method of claim 1, wherein the helmet layer is deposited by a plasma enhanced chemical vapor deposition (PECVD) technique, a plasma enhanced atomic layer deposition (PEALD) technique, or any combination thereof techniques.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
recessing the second dielectric layer;
depositing a screen layer on the recessed second dielectric layer;
removing the second dielectric layer through the screen layer to form an air gap; and
stuffing the screen layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising curing the second dielectric layer.

### Claim 6

A method to provide a maskless air gap flow, comprising:
etching a trench in a first dielectric layer between conductive features on a substrate, the trench having a bottom below a bottom of the conductive features;
depositing a helmet layer on the trench and the conductive features, the helmet layer directly on the conductive features;
depositing a second dielectric layer on the helmet layer on the trench;
depositing a screen layer on the second dielectric layer; and
removing the second dielectric layer through the screen layer for form an air gap.

### Claim 7 (depends on 6)

The method of claim 6, further comprising recessing the second dielectric layer, wherein the screen layer is deposited on the recessed second dielectric layer.

### Claim 8 (depends on 6)

The method of claim 6, further comprising stuffing the screen layer; and depositing an etch stop layer on the screen layer.

### Claim 9 (depends on 6)

The method of claim 6, wherein the helmet layer is deposited by a plasma enhanced chemical vapor deposition (PECVD) technique, a plasma enhanced atomic layer deposition (PEALD) technique, or any combination thereof techniques.

### Claim 10 (depends on 6)

The method of claim 6, wherein the helmet layer is free of oxygen.

### Claim 11

A method to provide a replacement interlayer dielectric flow, comprising:
etching a trench in a first dielectric layer between conductive features on a substrate, the trench having a bottom below a bottom of the conductive features;
depositing a helmet layer on the trench and the conductive features, the helmet layer directly on the conductive features;
depositing a second dielectric layer on the helmet layer; and
depositing an etch stop layer on the second dielectric layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the helmet layer is deposited by a plasma enhanced chemical vapor deposition (PECVD) technique, a plasma enhanced atomic layer deposition (PEALD) technique, or any combination thereof techniques.

### Claim 13 (depends on 11)

The method of claim 11, wherein the helmet layer is free of oxygen.

### Claim 14 (depends on 11)

The method of claim 11, further comprising curing the second dielectric layer, and removing a portion of the cured second dielectric layer to expose a portion of the helmet layer, wherein the etch stop layer is deposited on the portion of the helmet layer.

### Claim 15 (depends on 11)

The method of claim 11, further comprising depositing an interconnect layer on the etch stop layer.

### Claim 16

An electronic device, comprising a helmet layer on a plurality of conductive features on a first dielectric layer on a substrate;
a second dielectric layer on a first portion of the helmet layer on a trench between at least two of the conductive features; and
an etch stop layer on a second portion of the helmet layer, wherein the etch stop layer comprises a dielectric material.

### Claim 17 (depends on 16)

The electronic device of claim 16, wherein the second portion is on a top portion of the at least two of the conductive features.

### Claim 18 (depends on 16)

The electronic device of claim 16, wherein the thickness of the helmet layer is less than 5 nanometers.

### Claim 19 (depends on 16)

The electronic device of claim 16, wherein the helmet layer is free of oxygen.

### Claim 20 (depends on 16)

The electronic device of claim 16, further comprising an interconnect layer on the etch stop layer.