# US 10,483,157 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 10,483,157 B2
- Document ID: US10483157B2
- Status: Granted
- Kind: B2
- Application number: 16/049,715
- Filed: 2018-07-30
- Published: 2018-11-22
- Granted: 2019-11-19
- Earliest claimed: 2016-12-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Meng-Hsuan Hsiao; Yee-Chia Yeo; Tung Ying Lee; Chih Chieh Yeh
- Web page: https://patentgrep.com/patent/US10483157B2

## CPC

- H10W 20/081: {by forming openings in the dielectric parts}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/013: {of electrodes having a conductor capacitively coupled to a semiconductor by an insulator}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/834: {comprising FinFETs}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0696: {by using sacrificial placeholders, e.g. using sacrificial plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10B 12/056: {the transistor being a FinFET}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

## Claims

### Claim 1

A semiconductor device including fin field effect transistors (FinFETs), comprising:
a first FinFET including a first fin structure extending in a first direction, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure extending in the first direction, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure;
a dielectric layer separating the first source/drain contact and the second source/drain contact; and
a first liner layer, made of a different dielectric material than the dielectric layer, disposed between the dielectric layer and the first source/drain contact.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first liner layer is made of silicon nitride.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising an isolation insulating layer in which bottom portions of the first and second fin structures are embedded,
wherein a part of the first liner layer is disposed between the dielectric layer and the isolation insulating layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a second liner layer between the part of the first liner layer and the isolation insulating layer.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the second liner layer is made of silicon nitride.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, further comprising a residual piece of a semiconductor material disposed at a bottom corner of the dielectric layer.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the residual piece of the semiconductor material includes amorphous silicon or polysilicon.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first FinFET is a p-type and the second FinFET is an n-type.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein a width of at least one of the first source/drain contact and the second source/drain contact along a second direction crossing the first direction varies along a vertical direction perpendicular to a surface the substrate.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the width decreases as a distance from the substrate increases.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein:
at least one of the first and second source/drain contacts includes a lower portion and an upper portion having a funnel shape, and
a width of the upper portion is greater than a width of the bottom portion.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the width of the bottom portion is constant.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein a difference between the width of the upper portion and the width of the bottom portion is less than 6 nm.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, wherein a vertical length of the bottom portion is greater than a vertical length of the upper portion.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, wherein the vertical length of the bottom portion is twice or more the vertical length of the upper portion.

### Claim 16 (depends on 11)

The semiconductor device of claim 11, wherein:
the first FinFET further includes a gate electrode, and
an interface between the bottom portion and the upper portion is located at a level higher than an upper surface of the gate electrode.

### Claim 17 (depends on 4)

The semiconductor device of claim 4, wherein a width of the second liner layer along a second direction crossing the first direction is smaller than a width of the dielectric layer along the second direction.

### Claim 18 (depends on 4)

The semiconductor device of claim 4, wherein a width of the second liner layer along a second direction crossing the first direction is greater than a width of the dielectric layer along the second direction.

### Claim 19 (depends on 1)

The semiconductor device of claim 1, wherein the first source/drain structure includes an epitaxial layer formed around a source/drain region of the first fin structure.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the first source/drain structure further includes a silicide layer disposed between the epitaxial layer and the first source/drain contact.