# US 10,483,155 B2 · Trench isolation interfaces

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- Number: US 10,483,155 B2
- Document ID: US10483155B2
- Status: Granted
- Kind: B2
- Application number: 16/396,288
- Filed: 2019-04-26
- Published: 2019-08-15
- Granted: 2019-11-19
- Earliest claimed: 2017-07-05
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Arup Bhattacharyya
- Web page: https://patentgrep.com/patent/US10483155B2

## CPC

- H10W 10/50: Isolation regions based on field-effect
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10D 64/037: {comprising charge-trapping insulators}
- H10D 64/111: {Field plates}
- H10W 10/0148: {comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/051: {of isolation region based on field-effect}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure includes semiconductor structures and methods of forming semiconductor structures for trench isolation interfaces. An example semiconductor structure includes a semiconductor substrate having a shallow trench isolation (STI) structure with a trench formed therein. An material in the trench forms a charged interface by interaction with the semiconductor substrate of the STI structure. The formed charged interface raises a parasitic threshold of the STI structure.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming a shallow trench isolation (STI) structure in a polycrystalline silicon (polysilicon) substrate material;
depositing a layer of aluminum oxide (Al2O3) dielectric on vertical and horizontal surfaces of the STI structure to form a trench between the STI structure and a memory device;
forming an interface in the trench with a fixed negative charge by interaction of the polysilicon substrate material with the Al2O3 dielectric layer; and
thereby raising a parasitic threshold of the STI structure.

### Claim 2 (depends on 1)

The method of claim 1, further comprising reducing an edge fringing field intensity for the memory device.

### Claim 3 (depends on 1)

The method of claim 1, further comprising depositing a layer of injector silicon-rich nitride (IN-SRN) on a surface of the Al2O3 dielectric layer opposite from the interface.

### Claim 4 (depends on 1)

The method of claim 1, further comprising depositing a layer of injector silicon-rich nitride (IN-SRN) on a surface of the STI structure in the trench prior to deposition of the Al2O3 dielectric layer.

### Claim 5

A method of forming a semiconductor structure, comprising:
forming a trench in a semiconductor substrate to have a shallow trench isolation (STI) structure;
forming a charged interface in the trench by interaction of a material with the semiconductor substrate of the STI structure; and
raising, by the formed charged interface, a parasitic threshold of the STI structure.

### Claim 6 (depends on 5)

The method of claim 5, further comprising:
positioning a memory device interior to the trench of the STI structure and adjacent the trench; and
reducing, by the formed charged interface, an edge fringing field intensity for the memory device.

### Claim 7 (depends on 5)

The method of claim 5, further comprising reducing, by the formed charged interface, a rate of charge loss for the memory device.

### Claim 8 (depends on 5)

The method of claim 5, further comprising:
forming the material in the trench as an aluminum oxide (Al2O3) dielectric;
forming the semiconductor substrate of the STI structure as polycrystalline silicon outside the trench relative to a memory device formed interior to the trench; and
forming the charged interface is an aluminosilicate (AlSiOx) at an interface between the polycrystalline silicon of the STI structure and the Al2O3 dielectric.

### Claim 9 (depends on 8)

The method of claim 8, further comprising forming the AlSiOx to have a fixed negative charge with an electron density in a range of from around 1×1011 to around 5×1012 extra electrons per square centimeter at a uni-potential interface.

### Claim 10 (depends on 5)

The method of claim 5, further comprising:
forming the trench in a polycrystalline silicon substrate having the STI structure;
forming the charged interface to include an aluminum oxide (Al2O3) dielectric in the trench formed on a surface of the STI structure; and
forming a memory device with a portion positioned interior to the trench of the STI structure and adjacent the trench.

### Claim 11 (depends on 5)

The method of claim 5, further comprising forming an aluminum oxide (Al2O3) dielectric as the charged interface having a fixed negative charge by interaction with the polysilicon substrate.

### Claim 12 (depends on 5)

The method of claim 5, further comprising:
forming a silicon oxide (SiO2) dielectric in the trench formed on a surface of the STI structure; and
forming an aluminum oxide (Al2O3) dielectric on the SiO2 dielectric to have an interface with a fixed negative charge by interaction of the SiO2 dielectric with the Al2O3 dielectric.

### Claim 13 (depends on 5)

The method of claim 5, further comprising:
forming a memory device to have a polysilicon gate above the STI structure and wider than opposite walls of the trench; and
forming an extension layer of an aluminum oxide (Al2O3) dielectric layer of the trench between the STI structure and the polysilicon gate formed wider than the opposite walls of the trench.

### Claim 14 (depends on 5)

The method of claim 5, further comprising:
forming a floating gate of a memory device under a high k dielectric layer and between opposite walls of the trench formed from an aluminum oxide (Al2O3) dielectric; and
forming a tunnel layer under the floating gate and between the opposite walls of the trench formed from the Al2O3 dielectric.

### Claim 15 (depends on 5)

The method of claim 5, further comprising:
forming a floating plate from an injector silicon-rich nitride;
forming the floating plate under a high k dielectric layer and between opposite walls of the trench formed from an aluminum oxide (Al2O3) dielectric;
forming a tunnel layer under the floating plate and between the opposite walls of the trench formed from the Al2O3 dielectric; and
forming the tunnel layer between the floating plate and the semiconductor substrate.

### Claim 16

A method of forming a semiconductor structure, comprising:
forming a trench in a semiconductor substrate to have a shallow trench isolation (STI) structure;
forming an aluminum oxide (Al2O3) dielectric layer in the trench;
forming an injector silicon-rich nitride (IN-SRN) layer on a surface of the trench opposite from the semiconductor substrate of the STI structure and adjacent the Al2O3 dielectric layer; and
raising a parasitic threshold of the STI structure by a charged interface formed from a composite of the Al2O3 dielectric layer and the IN-SRN layer.

### Claim 17 (depends on 16)

The method of claim 16, further comprising the Al2O3 dielectric layer contributing to formation of a charged interface with a fixed negative charge by interaction with the semiconductor substrate formed from polysilicon.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
forming a silicon oxide (SiO2) dielectric layer in the trench on a surface of the STI structure;
forming the Al2O3 dielectric layer upon the SiO2 dielectric layer; and
contributing to formation of a charged interface with a fixed negative charge by a composite of the SiO2 dielectric layer and the Al2O3 dielectric layer.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
positioning a memory device interior to the trench of the STI structure and adjacent the IN-SRN layer; and
reducing an edge fringing field intensity for the memory device by the composite of the Al2O3 dielectric layer and the IN-SRN layer.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
positioning a memory device interior to the trench of the STI structure and adjacent the IN-SRN layer;
positioning a channel of the memory device interior to the IN-SRN layer; and
positioning the channel to have a width and a length perpendicular to the IN-SRN layer on the surface of the trench.