# US 10,483,153 B2 · Deep trench isolation structure in semiconductor device

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- Number: US 10,483,153 B2
- Document ID: US10483153B2
- Status: Granted
- Kind: B2
- Application number: 15/885,524
- Filed: 2018-01-31
- Published: 2019-05-16
- Granted: 2019-11-19
- Earliest claimed: 2017-11-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Hua Yen; Ching-Hung Kao; Po-Jen Wang; Tsung-Han Tsai
- Web page: https://patentgrep.com/patent/US10483153B2

## CPC

- H10P 90/1906: {Preparing SOI wafers}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10P 50/283: {by chemical means}
- H10P 50/642: {Chemical etching}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/021: {of air gaps}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 10/20: Air gaps
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/2041: {Photolithographic processes}
- H10P 95/062: {involving a dielectric removal step}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An integrated circuit includes a semiconductor substrate, an isolation region, a first active component and at least one deep trench isolation structure. The isolation region is in the semiconductor substrate. The first active component is on the semiconductor substrate. The deep trench isolation structure extends from a bottom of the isolation region toward a bottom of the semiconductor substrate. The deep trench isolation structure has at least one air void therein.

## Claims

### Claim 1

An integrated circuit comprising:
a semiconductor substrate, wherein the semiconductor substrate is a semiconductor on insulator (SOI) substrate comprising a handle substrate, a semiconductor layer over the handle substrate, and a buried insulator layer between the handle substrate and the semiconductor layer;
an isolation region in the semiconductor substrate;
a first active component on the semiconductor layer of the semiconductor substrate; and
at least one deep trench isolation structure extending from a bottom of the isolation region toward a bottom of the semiconductor substrate, the deep trench isolation structure having at least one air void therein.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, wherein a top of the air void is lower than an interface between the semiconductor layer and the buried insulator layer.

### Claim 3 (depends on 1)

The integrated circuit of claim 1, wherein a bottom of the air void is lower than an interface between the buried insulator layer and the handle substrate.

### Claim 4 (depends on 1)

The integrated circuit of claim 1, wherein the deep trench isolation structure and the buried insulator layer comprise a same material.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, further comprising:
an interlayer dielectric (ILD) layer over the first active component, wherein the ILD layer and the deep trench isolation structure comprise a same material.

### Claim 6 (depends on 1)

The integrated circuit of claim 1, further comprising:
a second active component, wherein the isolation region is between the first active component and the second active component.

### Claim 7

An integrated circuit comprising:
a semiconductor substrate, wherein the semiconductor substrate is a semiconductor on insulator (SOI) substrate comprising a handle substrate, a semiconductor layer over the handle substrate, and a buried insulator layer between the handle substrate and the semiconductor layer;
an isolation region in the semiconductor substrate; and
a plurality of deep trench isolation structures extending from a bottom of the isolation region toward a bottom of the semiconductor substrate.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, wherein a portion of the handle substrate separates the deep trench isolation structures from each other.

### Claim 9 (depends on 7)

The integrated circuit of claim 7, wherein each of the deep trench isolation structures has at least one air void therein.

### Claim 10 (depends on 7)

The integrated circuit of claim 7, wherein the deep trench isolation structures resemble a shape of comb.

### Claim 11 (depends on 7)

The integrated circuit of claim 7, further comprising:
a gate strip over the semiconductor substrate, wherein at least one of the deep trench isolation structures and the gate strip have lengthwise directions substantially parallel to each other.

### Claim 12

An integrated circuit comprising:
a semiconductor substrate;
an isolation region in the semiconductor substrate;
at least one pillar extending from a bottom of the isolation region toward a bottom of the semiconductor substrate, the pillar tapering in a first direction away from the bottom of the semiconductor substrate; and
a plurality of deep trench isolation structures respectively on opposite sidewalls of the pillar.

### Claim 13 (depends on 12)

The integrated circuit of claim 12, wherein the pillar has a same material as the semiconductor substrate.

### Claim 14 (depends on 12)

The integrated circuit of claim 12, wherein the pillar comprises a semiconductor layer and an insulator layer over the semiconductor layer.

### Claim 15 (depends on 12)

The integrated circuit of claim 12, wherein a number of the at least one pillar is plural, and the pillars and the deep trench isolation structures are arranged in an alternating manner.

### Claim 16 (depends on 12)

The integrated circuit of claim 12, wherein the deep trench isolation structures taper in a second direction opposite the first direction.

### Claim 17 (depends on 12)

The integrated circuit of claim 12, wherein the deep trench isolation structures comprise air voids therein, and tops of the air voids are lower than a top of the pillar.

### Claim 18 (depends on 1)

The integrated circuit of claim 1, wherein the deep trench isolation structure extends through the buried insulator layer of the SOI substrate.

### Claim 19 (depends on 7)

The integrated circuit of claim 7, wherein the deep trench isolation structures extend through the semiconductor layer of the SOI substrate.

### Claim 20 (depends on 12)

The integrated circuit of claim 12, wherein the semiconductor substrate is a semiconductor on insulator (SOI) substrate.