# US 10,483,150 B2 · Apparatus for stacking semiconductor chips in a semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,150 B2 - Document ID: US10483150B2 - Status: Granted - Kind: B2 - Application number: 15/349,327 - Filed: 2016-11-11 - Published: 2017-08-17 - Granted: 2019-11-19 - Earliest claimed: 2016-02-11 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Gun-Ah Lee; Ji-Hwan Hwang; Cha-Jea Jo; Dong-Han Kim; Seung-Kon Mok - Web page: https://patentgrep.com/patent/US10483150B2 ## CPC - H10P 72/78: using vacuum or suction, e.g. Bernoulli chucks - H10W 72/0711: {Apparatus therefor} - H10P 72/0446: {Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates} - H10W 70/655: Fan-out layouts - H10W 72/07178: {Means for aligning} - H10W 72/07183: {Means for monitoring} - H10W 72/07207: {Temporary substrates, e.g. removable substrates} - H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate} - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/00: Package configurations - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract An apparatus for stacking semiconductor chips includes a push member configured to apply pressure to a semiconductor chip disposed on a substrate. The push member includes a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate. The push plate includes a central portion having an area smaller than an area of an upper side of the semiconductor chip, and a plurality of protrusions disposed at respective ends of the central portion. ## Claims ### Claim 1 An apparatus for stacking semiconductor chips, comprising: a push member configured to apply pressure to a semiconductor chip disposed on a substrate, and wherein the push member comprises a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate, wherein the push plate comprises: a central portion having an area smaller than an area of an upper side of the semiconductor chip; and a plurality of protrusions disposed at corners of the central portion, and each of the plurality of protrusions protrudes over two adjacent edges of the central portion of the push plate, wherein a modulus of elasticity of the plurality of protrusions is higher than a modulus of elasticity of the central portion. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the central portion of the push plate has a polygon shape, at least two of the plurality of protrusions have a same shape as each other. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the central portion of the push plate includes one or more concave portions. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the push plate includes a resilient material. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein a first length from a center of the push plate to a furthermost corner of a first protrusion of the plurality of protrusions is greater than a second length from a center of the upper side of the semiconductor chip to a corner of the semiconductor chip. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein when overlapping the push plate with the semiconductor chip, an area formed by edges of the central portion of the push plate fully overlaps an upper portion of the semiconductor chip, and at least one of the plurality of protrusions partially overlaps the upper portion of the semiconductor chip. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the push plate has a symmetrical structure with respect to the push rod. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein each of the plurality of protrusions of the push plate has a circular shape. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the push plate is configured to apply a same pressure to a central portion of the upper side of the semiconductor chip and to corner portions of the upper side of the semiconductor chip. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the protrusions are upwardly protruded from a surface of the push plate, and wherein the protrusions and the push rod are attached on the same surface of the push plate. ### Claim 11 (depends on 1) The apparatus for stacking semiconductor chips of claim 1, wherein an area of direct contact between the push plate and an upper surface of the semiconductor chip is smaller than the area of the upper surface of the semiconductor chip. ### Claim 12 An apparatus for stacking semiconductor chips to be mounted on a substrate, each of the semiconductor chips comprising a joining member at a lower portion of the chip, the apparatus being configured to apply pressure to the semiconductor chips to connect the semiconductor chips to the substrate or to connect the semiconductor chips to each other, the apparatus comprising: a stage on which the substrate is disposed, wherein the semiconductor chips are stacked on the substrate; a push member that faces the stage and is configured to apply pressure to each of the semiconductor chips; and a pressure gauge configured to measure the pressure applied to the semiconductor chips by the push member, wherein the push member comprises a push plate configured to contact at least one of the semiconductor chips and a push rod connected to the push plate, and wherein an area of a central portion of the push plate is smaller than an area of an upper side of the at least one of the semiconductor chips, wherein the central portion of the push plate at least partially overlaps the semiconductor chip, and wherein a plurality of protrusions is disposed at corners of the central portion of the push plate, and herein a modulus of elasticity of the plurality of protrusions is higher than a modulus of elasticity of the central portion. ### Claim 13 (depends on 12) The apparatus of claim 12, further comprising a controller configured to adjust the pressure applied to the at least one of the semiconductor chips by the push member. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the pressure applied to the push plate is adjusted by the controller while the push member applies a pressure to the at least one of the semiconductor chips such that a central portion of the upper side of the at least one of the semiconductor chips and corners of the upper side of the at least one of the semiconductor chips are subjected to substantially the same pressure by the push plate. ### Claim 15 (depends on 12) The apparatus of claim 12, wherein an area of the push plate which contacts the upper side of the at least one of the semiconductor chips is a flat surface. ### Claim 16 An apparatus for stacking semiconductor chips, comprising: a push member configured to apply pressure to a semiconductor chip, wherein the semiconductor chip is disposed on a substrate, and wherein the push member comprises a push plate configured to contact the semiconductor chip, and a push rod connected to the push plate, wherein, the push plate comprises: a flat first portion; and two or more flat second portions disposed at ends of the flat first portion, wherein the flat first portion includes a curved part and one of the two or more flat second portions is disposed at a first end of the curved part, wherein the push plate is configured such that when the push member applies the pressure to the semiconductor chip, the flat first portion of the push plate is fully overlapped by the semiconductor chip, and each of the two or more flat second portions at least partially overlap the semiconductor chip, wherein a modulus of elasticity of the flat first portion is lower than a modulus of elasticity of the two or more flat second portions. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the one of the two or more flat second portions hangs over the semiconductor chip. ### Claim 18 (depends on 16) The apparatus of claim 16, wherein, in plan view, the flat first portion is smaller than the semiconductor chip. ### Claim 19 (depends on 16) The apparatus of claim 16, wherein the push rod is disposed at a center of the flat first portion.