# US 10,483,148 B2 · Protective tape and method for manufacturing semiconductor device

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- Number: US 10,483,148 B2
- Document ID: US10483148B2
- Status: Granted
- Kind: B2
- Application number: 15/765,358
- Filed: 2016-10-18
- Published: 2018-10-04
- Granted: 2019-11-19
- Earliest claimed: 2015-10-19
- Assignees: Dexerials Corporation
- Applicants: Dexerials Corporation
- Inventors: Hironobu Moriyama
- Web page: https://patentgrep.com/patent/US10483148B2

## CPC

- H10P 72/7402: {Wafer tapes, e.g. grinding or dicing support tapes}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/7404: {the wafer tape being a laminate of three or more layers, e.g. including additional layers beyond a base layer and an uppermost adhesive layer}
- H10W 74/01: Manufacture or treatment
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 74/40: characterised by their materials
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/742: {involving stretching of the auxiliary support post dicing}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/7438: {with parts of the auxiliary support remaining in the finished device}
- H10P 72/7442: {Separation by peeling}
- H10W 72/012: {of bump connectors, dummy bumps or thermal bumps}
- H10W 72/01271: {Cleaning, e.g. oxide removal or de-smearing}
- H10W 72/01304: {using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07234: {Using a reflow oven}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/354: {comprising polymers}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A protective tape including an adhesive agent layer, a thermoplastic resin layer, and a matrix film layer in this order to a surface of a wafer on which a bump electrode is formed; grinding a surface of the wafer opposite to the surface on which the protective tape is pasted; pasting an adhesive tape to the ground surface of the wafer; peeling the protective tape so that the adhesive agent layer remains and other layers are removed; dicing the wafer to which the adhesive tape is pasted to obtain individual semiconductor chips; and curing the adhesive agent layer before dicing; the adhesive agent layer after curing has a shear storage modulus of 3.0E+08 Pa to 5.0E+09 Pa, and the ratio of the thickness of the adhesive agent layer of the protective tape before pasting to the height of the bump electrode is 1/30 to 1/6.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, the method comprising:
pasting a protective tape to a surface of a wafer on which a bump electrode is formed, the protective tape having an adhesive agent layer, a thermoplastic resin layer, and a matrix film layer in this order;
grinding a surface of the wafer opposite to the surface on which the protective tape is pasted;
pasting an adhesive tape to the ground surface of the wafer;
peeling the protective tape so that the adhesive agent layer remains and other layers are removed;
dicing the wafer to which the adhesive tape is pasted to obtain individual semiconductor chips; and
curing the adhesive agent layer before dicing, wherein:
the adhesive agent layer after curing has a shear storage modulus of 3.0E+08 Pa to 5.0E+09 Pa, and
the ratio of the thickness of the adhesive agent layer of the protective tape before pasting to the height of the bump electrode is 1/30 to 1/6.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
the adhesive agent layer is formed using an adhesive agent composition, and
the adhesive agent composition contains a film-forming resin, a thermosetting resin, a curing agent, and a filler, and the content of the filler in the adhesive agent composition is 3 to 35% by mass.

### Claim 3 (depends on 1)

The method according to claim 1, wherein:
the adhesive agent layer is formed using an adhesive agent composition, and
the adhesive agent composition contains a film-forming resin, a thermosetting resin, a curing agent, and a filler, and the content of the filler in the adhesive agent composition is 25 to 35% by mass.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the thickness of the adhesive agent layer of the protective tape before pasting is 10 to 30 μm.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the height of the bump electrode is 100 to 300 μm.

### Claim 6 (depends on 1)

The method according to claim 1, further comprising bonding the individual semiconductor chip and a substrate having an electrode with flux in a reflow oven, wherein the bump electrode of the individual semiconductor chip is a solder bump.

### Claim 7 (depends on 2)

The method according to claim 2, wherein the thickness of the adhesive agent layer of the protective tape before pasting is 10 to 30 μm.

### Claim 8 (depends on 3)

The method according to claim 3, wherein the thickness of the adhesive agent layer of the protective tape before pasting is 10 to 30 μm.

### Claim 9 (depends on 2)

The method according to claim 2, wherein the height of the bump electrode is 100 to 300 μm.

### Claim 10 (depends on 3)

The method according to claim 3, wherein the height of the bump electrode is 100 to 300 μm.

### Claim 11 (depends on 4)

The method according to claim 4, wherein the height of the bump electrode is 100 to 300 μm.

### Claim 12 (depends on 2)

The method according to claim 2, further comprising bonding the individual semiconductor chip and a substrate having an electrode with flux in a reflow oven, wherein the bump electrode of the individual semiconductor chip is a solder bump.

### Claim 13 (depends on 3)

The method according to claim 3, further comprising bonding the individual semiconductor chip and a substrate having an electrode with flux in a reflow oven, wherein the bump electrode of the individual semiconductor chip is a solder bump.

### Claim 14 (depends on 4)

The method according to claim 4, further comprising bonding the individual semiconductor chip and a substrate having an electrode with flux in a reflow oven, wherein the bump electrode of the individual semiconductor chip is a solder bump.

### Claim 15 (depends on 5)

The method according to claim 5, further comprising bonding the individual semiconductor chip and a substrate having an electrode with flux in a reflow oven, wherein the bump electrode of the individual semiconductor chip is a solder bump.