# US 10,483,133 B2 · Method for fabricating a semiconductor chip panel > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,133 B2 - Document ID: US10483133B2 - Status: Granted - Kind: B2 - Application number: 15/944,306 - Filed: 2018-04-03 - Published: 2018-08-09 - Granted: 2019-11-19 - Earliest claimed: 2013-01-14 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Daniel Porwol; Edward Fuergut - Web page: https://patentgrep.com/patent/US10483133B2 ## CPC - H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue} - H10W 72/0198: {batch processes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/01: Manufacture or treatment - H10W 74/014: {using batch processing} - H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/073: {of die-attach connectors} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/111: {the semiconductor body being completely enclosed} - H10W 74/114: {by a substrate and the encapsulations} - H10W 90/10: Configurations of laterally-adjacent chips - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on a carrier with the second main faces facing the carrier and applying an encapsulation material by transfer molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not. ## Claims ### Claim 1 A method for fabricating a semiconductor chip panel, the method comprising: providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces; providing an adhesive layer located on a carrier; placing at least one interposer on the adhesive layer located on the carrier; placing the semiconductor chips on the at least one interposer with the second main faces facing the carrier; and applying an encapsulation material by molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not. ### Claim 2 (depends on 1) The method according to claim 1, further comprising covering the first main faces of the plurality of semiconductor chips with a release film before applying the encapsulation material. ### Claim 3 (depends on 2) The method according to claim 2, wherein the release film comprises a thermoplastic foil. ### Claim 4 (depends on 1) The method according to claim 1, wherein the semiconductor chips comprise one or more of a power transistor, a vertical transistor, a MOS transistor, an insulated gate bipolar transistor, a logic circuit, a sensor, or a passive component. ### Claim 5 (depends on 1) The method according to claim 1, wherein the semiconductor chips comprise different electrical devices. ### Claim 6 (depends on 1) The method according to claim 1, wherein applying the encapsulation material comprises forming a protruding stabilization ring around the semiconductor chip panel for stabilizing the semiconductor chip panel. ### Claim 7 (depends on 1) The method according to claim 1, further comprising removing the carrier thereby exposing the second main faces of the semiconductor chips. ### Claim 8 (depends on 1) The method according to claim 1, wherein the semiconductor chips comprise one or more electrical contact elements only on the first main face. ### Claim 9 (depends on 1) The method according to claim 1, wherein the semiconductor chips comprise one or more electrical contact elements only on the second main face. ### Claim 10 (depends on 1) The method according to claim 1, wherein the semiconductor chips comprise one or more electrical contacts on the first main face and one or more electrical contacts on the second main face. ### Claim 11 (depends on 1) The method according to claim 1, wherein each interposer is a lead frame. ### Claim 12 (depends on 2) The method according to claim 2, wherein the release film comprises a polymer foil. ### Claim 13 A method for fabricating a semiconductor chip panel, the method comprising: providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces; placing the semiconductor chips on a carrier with the second main faces facing the carrier; covering the first main faces of the plurality of semiconductor chips with a release film before applying an encapsulation material; and applying the encapsulation material by molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not. ### Claim 14 (depends on 13) The method according to claim 13, wherein the release film comprises a thermoplastic foil. ### Claim 15 (depends on 13) The method according to claim 13, wherein the release film comprises a polymer foil. ### Claim 16 (depends on 13) The method according to claim 13, wherein the molding is a transfer molding. ### Claim 17 (depends on 13) The method according to claim 13, further comprising removing the carrier thereby exposing the second main faces of the semiconductor chips. ### Claim 18 A method for fabricating a semiconductor chip panel, the method comprising: providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces; placing the semiconductor chips on a carrier with the second main faces facing the carrier; placing a release film directly on the first main faces of the plurality of semiconductor chips before applying an encapsulation material; applying the encapsulation material by molding spaces between the release film and the carrier; and removing the release film thereby forming the semiconductor chip panel. ### Claim 19 (depends on 18) The method according to claim 18, wherein the release film comprises a thermoplastic foil or a polymer foil. ### Claim 20 (depends on 18) The method according to claim 18, further comprising removing the carrier thereby exposing the second main faces of the semiconductor chips.