# US 10,483,125 B2 · Semiconductor device and method for manufacturing same

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- Number: US 10,483,125 B2
- Document ID: US10483125B2
- Status: Granted
- Kind: B2
- Application number: 16/114,303
- Filed: 2018-08-28
- Published: 2018-12-20
- Granted: 2019-11-19
- Earliest claimed: 2017-02-10
- Assignees: TowerJazz Panasonic Semiconductor Co., Ltd.
- Applicants: Towerjazz Panasonic Semiconductor Co., Ltd.
- Inventors: Yuka Inoue; Mitsunori Fukura; Nobuyoshi Takahashi; Masahiro Oda; Hisashi Yano; Yutaka Ito; Yasunori Morinaga
- Web page: https://patentgrep.com/patent/US10483125B2

## CPC

- H10P 14/40: of conductive or resistive materials
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0238: {comprising etching via holes through pads or through electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/085: {involving intermediate temporary filling with material}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first interlayer film formed on an upper surface of a substrate, a first metal wiring line, a second interlayer film, a second metal wiring line, a first via electrically connecting the first metal wiring line and the second metal wiring line, a landing pad embedded in an upper portion of the first interlayer film and penetrating the second interlayer film, and a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad. The lower surface position of the landing pad is different from that of the first metal wiring line.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate provided with a first region and a second region;
a first interlayer film formed on an upper surface of the substrate;
a first metal wiring line embedded in an upper portion of the first interlayer film in the first region;
a second interlayer film formed on the first interlayer film and the first metal wiring line;
a second metal wiring line embedded in an upper portion of the second interlayer film in the first region;
a first via penetrating the second interlayer film and electrically connecting the first metal wiring line and the second metal wiring line;
a landing pad embedded in the upper portion of the first interlayer film and penetrating the second interlayer film in the second region; and
a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad in the second region,
wherein a lower surface position of the landing pad is different from that of the first metal wiring line.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
the first via and the second metal wiring line are made of an identical material, and
the landing pad has a metal film provided from the upper portion of the first interlayer film to an inside of the second interlayer film and made of an identical material to those of the first via and the second metal wiring line.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
the lower surface position of the landing pad is lower than that of the first metal wiring line, and
a thickness of the landing pad is thicker than a sum of a height of the first metal wiring line, a height of the first via, and a height of the second metal wiring line.

### Claim 4

A method for manufacturing a semiconductor device, comprising:
a step of forming a first interlayer film formed on an upper surface of a substrate provided with a first region and a second region and a first metal wiring line embedded in an upper portion of the first interlayer film;
a step of forming a second interlayer film formed on the first interlayer film and the first metal wiring line;
a step of forming, in the first region, a wiring groove in the second interlayer film and a first via hole penetrating the second interlayer film above the first metal wiring line;
a step of forming, in the second region, a pad recessed portion at the upper portion of the first interlayer film and forming a pad hole penetrating the second interlayer film upon formation of the wiring groove and the first via hole;
a step of filling the first via hole, the wiring groove, the pad recessed portion, and the pad hole with metal to form a first via in the first via hole, form a second metal wiring line in the wiring groove, and form a landing pad in the pad recessed portion and the pad hole; and
a step of forming, in the second region, a second via penetrating the substrate and the first interlayer film from a back side of the substrate and connected to the landing pad.

### Claim 5 (depends on 4)

The semiconductor device manufacturing method according to claim 4, wherein
the pad hole is formed in parallel with formation of the first via hole, and
at least part of the pad recessed portion is formed in parallel with formation of the wiring groove.

### Claim 6 (depends on 4)

The semiconductor device manufacturing method according to claim 4, further comprising:
a step of forming a liner film made of an insulator on the first metal wiring line and the first interlayer film before the step of forming the second interlayer film and after the step of forming the first metal wiring line,
wherein the pad hole is formed in parallel with formation of the first via hole, and
the pad recessed portion is formed in the second region in parallel with removal of a portion of the liner film exposed through the first via hole.

### Claim 7 (depends on 4)

The semiconductor device manufacturing method according to claim 4, wherein
a lower surface height of the first metal wiring line and a lower surface height of the landing pad are different from each other.

### Claim 8 (depends on 4)

The semiconductor device manufacturing method according to claim 4, wherein
at the step of forming the first via hole, a third via having a larger diameter than that of the first via is formed at the second interlayer film in the second region.