# US 10,483,124 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,124 B2 - Document ID: US10483124B2 - Status: Granted - Kind: B2 - Application number: 16/126,055 - Filed: 2018-09-10 - Published: 2019-07-11 - Granted: 2019-11-19 - Earliest claimed: 2018-01-11 - Assignees: Toshiba Memory Corporation - Applicants: Toshiba Memory Corporation - Inventors: Masakazu Sawano; Takahiro Tomimatsu; Junichi Shibata; Hideki Inokuma; Hisashi Kato; Kenta Yoshinaga - Web page: https://patentgrep.com/patent/US10483124B2 ## CPC - H10P 50/73: {using masks for insulating materials} - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/40: characterised by the peripheral circuit region - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10P 50/283: {by chemical means} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract According to one embodiment, a semiconductor device includes: a first stack above a substrate and including insulation layers and conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end portion of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including first and second layers stacked in the first direction. In the second and/or third direction, a dimension of the first stack is larger than a dimension of the second stack. ## Claims ### Claim 1 A semiconductor device comprising: a substrate; a first stack above the substrate and including first insulation layers and first conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end part of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the first conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and at least one second stack above the substrate and including at least one first layer and at least one second layer stacked in the first direction, wherein, in the at least one of the second direction and the third direction, a first dimension of the first stack is larger than a second dimension of the second stack. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a third stack above the substrate and including at least one third layer and at least one fourth layer stacked in the first direction, the third stack being aligned with the second stack along the third direction. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein a first distance in the second direction from an arc-shape step of the steps to the second stack differs from a second distance in the second direction from the arc-shape step to the third stack. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein the second stack is provided above a side of an end portion of the substrate in the third direction, the third stack is provided above a side of a center portion of the substrate in the third direction, and the first distance is smaller than the second distance. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the first stack includes a first block and a second block aligned along the third direction, the first block and the second block each include a first end portion in the second direction and a second end portion opposite the first end portion in the second direction, in the first block, a first contact is provided on a side of the first end portion, and the second stack is provided on a side of the second end portion, and in the second block, the second stack is provided on a side of the first end portion, and a second contact is provided on a side of the second end portion. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, further comprising: a fourth stack above the substrate and including at least one fifth layer and at least one sixth layer stacked in the first direction, the fourth stack being aligned with the second stack along the second direction. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the second stack is provided externally in the second direction to the part of the steps having the arc shape of the first stack. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the second stack is provided on the staircase-shaped portion of the first stack. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the second stack is provided on a first step of the steps and includes a second step aligned with the second step. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the second stack is provided on a lowermost one of the terraces aligned along the third direction. ### Claim 11 A semiconductor device comprising: a substrate; a first stack above the substrate and including first insulation layers and first conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end part of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the first conductive layers; at least one second stack above the substrate and including at least one first layer and at least one second layer stacked in the first direction; and a third stack above the substrate and including at least one third layer and at least one fourth layer stacked in the first direction, the third stack being aligned with the second stack along a third direction crossing the second direction, wherein a first dimension of the first stack in the third direction is larger than a second dimension of the second stack in the third direction and a third dimension of the third stack in the third direction, and/or a first number of stacked layers of the first stack in the first direction is greater than a second number of stacked layers of the second stack in the first direction and a third number of stacked layers of the third stack in the first direction. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the first stack includes a first block and a second block aligned along the third direction, the first block and the second block each include a first end portion in the second direction and a second end portion opposite the first end portion in the second direction, in the first block, a first contact is provided on a side of the first end portion, and the second stack is provided on a side of the second end portion, and in the second block, the second stack is provided on a side of the first end portion, and a second contact is provided on a side of the second end portion. ### Claim 13 (depends on 11) The semiconductor device according to claim 11, further comprising: a fourth stack above the substrate and including at least one fifth layer and at least one sixth layer stacked in the first direction, the fourth stack being aligned with the second stack along the second direction. ### Claim 14 (depends on 11) The semiconductor device according to claim 11, wherein the second stack and the third stack each is a region provided so as to project in the first direction in both ends thereof in the second direction. ### Claim 15 (depends on 11) The semiconductor device according to claim 11, wherein the second stack and the third stack are provided on the staircase-shaped portion of the first stack. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein the second stack and the third stack are provided on a first step of the steps and each includes a second step aligned with the first step. ### Claim 17 A semiconductor device comprising: a substrate; a first stack above the substrate and including first insulation layers and first conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end part of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the first conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and a second stack above the substrate and including at least one first layer and at least one second layer stacked in the first direction, wherein a first number of stacked layers of the first stack in the first direction is greater than a second number of stacked layers of the second stack in the first direction. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, further comprising: a third stack above the substrate and including at least one third layer and at least one fourth layer stacked in the first direction, the third stack being aligned with the second stack along the third direction. ### Claim 19 (depends on 17) The semiconductor device according to claim 17, further comprising: a fourth stack above the substrate and including at least one fifth layer and at least one sixth layer stacked in the first direction, the fourth stack being aligned with the second stack along the second direction. ### Claim 20 (depends on 17) The semiconductor device according to claim 17, wherein the second stack is provided on a lowermost one of the terraces aligned along the third direction.