# US 10,483,121 B2 · Embedded memory in back-end-of-line low-k dielectric

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- Number: US 10,483,121 B2
- Document ID: US10483121B2
- Status: Granted
- Kind: B2
- Application number: 15/993,608
- Filed: 2018-05-31
- Published: 2018-10-04
- Granted: 2019-11-19
- Earliest claimed: 2017-02-15
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Lei Wang; Chim Seng Seet; Kai Hung Alex See
- Web page: https://patentgrep.com/patent/US10483121B2

## CPC

- H10P 95/062: {involving a dielectric removal step}
- H10N 50/01: Manufacture or treatment
- H10W 20/092: {by smoothing the dielectric parts}
- H10N 50/10: Magnetoresistive devices
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A low-k dielectric layer, such as SiCOH, with high and stable chemical mechanical polishing (CMP) removal rate (RR) is disclosed. The polishing rate enhancer (PRE) is disposed on the low-k dielectric layer. The PRE increases the CMP RR during CMP. Furthermore, the PRE stabilizes the increases CMP RR. This is particularly useful, for example, for memory applications in which the storage unit is formed in a low-k back-end-of-line (BEOL) dielectric layer. For example, the topography created can be quickly planarized by CMP while producing a uniform polished surface of the low-k dielectric layer due to the shortened processing time.

## Claims

### Claim 1

A device comprising:
a substrate comprising circuit components disposed on a substrate surface;
a plurality of interlevel dielectric (ILD) levels disposed on the substrate over the circuit components, wherein the plurality of interlevel dielectric (ILD) levels include a cell dielectric layer;
a storage unit of a memory cell between two adjacent ILD layers, wherein the storage unit is formed in the cell dielectric layer, the cell dielectric layer is disposed between the two adjacent ILD layers, the cell dielectric layer comprises a low-k dielectric material and is disposed over the storage unit; and
a polishing rate enhancer layer over the cell dielectric layer, the polishing rate enhancer layer comprising an oxide layer.

### Claim 2 (depends on 1)

The device of claim 1 wherein the storage unit comprises a magnetic tunnel junction (MTJ) of a magnetoresistive random access memory (MRAM) cell.

### Claim 3 (depends on 1)

The device of claim 1 wherein the low-k cell dielectric layer comprises SiCOH.

### Claim 4 (depends on 1)

The device of claim 1 wherein the plurality of ILD levels comprises:
x ILD levels, wherein each ILD layer includes
a contact level Vi−1 where I is the ith ILD level of the x ILD levels,
a metal level Mi where I is the ith ILD level of the x ILD levels disposed over the contact level; and
wherein the two adjacent ILD levels between which the storage unit is disposed comprises
an upper metal level Mj, which is a jth level of the x ILD levels, and
a lower metal level Mj−1.

### Claim 5 (depends on 4)

The device of claim 4 comprises:
a cap layer disposed over the lower metal level Mj−1;
a cell via dielectric layer disposed over the cap layer, wherein the cap layer and the cell via dielectric layer form a lower cell via layer; and
a lower storage unit contact plug disposed in the lower cell via layer.

### Claim 6 (depends on 5)

The device of claim 5 wherein the cap layer comprises SiCNH.