# US 10,483,120 B2 · Hybrid double patterning method for semiconductor manufacture

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,483,120 B2
- Document ID: US10483120B2
- Status: Granted
- Kind: B2
- Application number: 16/393,339
- Filed: 2019-04-24
- Published: 2019-08-15
- Granted: 2019-11-19
- Earliest claimed: 2017-09-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Ken-Hsien Hsieh; Wen-Li Cheng; Dong-Yo Jheng; Chih-Ming Lai; Ru-Gun Liu
- Web page: https://patentgrep.com/patent/US10483120B2

## CPC

- H10P 50/696: {Process specially adapted to improve the resolution of the mask}
- G03F 1/70: Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
- G03F 7/70425: {Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning}
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of fabricating an integrated circuit (IC) uses a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution. The method includes deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution. The method further includes classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.

## Claims

### Claim 1

A method of fabricating an integrated circuit (IC) with a first lithography technique having a first resolution and a second lithography technique having a second resolution lower than the first resolution, comprising:
deriving a graph from an IC layout, the graph having vertices and edges that connect some of the vertices, the vertices representing IC patterns in the IC layout, the edges representing spacing between the IC patterns that are smaller than the second resolution; and
classifying the edges into at least two types, a first type of edges representing spacing that is smaller than the first resolution, a second type of edges representing spacing that is equal to or greater than the first resolution but smaller than the second resolution.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
checking if the graph has a loop formed by odd number of vertices connected by edges of the first type.

### Claim 3 (depends on 2)

The method of claim 2, on condition that such loop exists, further comprising:
modifying the IC layout to break the loop.

### Claim 4 (depends on 2)

The method of claim 2, on condition that such loop does not exist, further comprising:
identifying vertices that correspond to the IC patterns to be patterned by the first lithography technique.

### Claim 5 (depends on 4)

The method of claim 4, wherein the identifying includes:
coloring vertices that are connected by edges of the first type with a first color and a second color different from the first color, wherein two vertices connected by a common edge of the first type are assigned with different colors.

### Claim 6 (depends on 5)

The method of claim 5, wherein the identifying further includes:
after the coloring, checking if there are two pairs of vertices in the graph such that the two pairs of vertices are connected through edges of the first type, a first pair of the two pairs are assigned with the first color and are connected directly by an edge of the second type, and a second pair of the two pairs are assigned with the second color and are connected directly by another edge of the second type.

### Claim 7 (depends on 6)

The method of claim 6, wherein the identifying further includes:
on condition that such pairs of vertices exist in the graph, relocating the IC patterns corresponding to the two pairs of vertices in the IC layout.

### Claim 8 (depends on 6)

The method of claim 6, wherein the identifying further includes:
on condition that such pairs of vertices do not exist in the graph, indicating that each pair of vertices that are assigned with a same color and are connected directly by an edge of the second type correspond to the IC patterns to be patterned by the first lithography technique.

### Claim 9 (depends on 4)

The method of claim 4, wherein the identifying includes:
finding a pair of vertices connected to by an edge of the second type; and
checking if there is a path connecting the pair of vertices using even number of edges of the first type.

### Claim 10 (depends on 9)

The method of claim 9, wherein the identifying further includes:
on condition that such path exists, indicating that the pair of vertices correspond to the IC patterns to be patterned by the first lithography technique.

### Claim 11

A method of fabricating an integrated circuit (IC) with a first lithography technique and a second lithography technique having a lower resolution than the first lithography technique, comprising:
providing a layout of the IC, the layout having a set of IC patterns;
deriving a graph from the layout by representing the IC patterns with vertices and representing spacing between IC patterns with edges connecting the corresponding vertices;
classifying the edges into two types, a first type of edges representing spacing that cannot be resolved by the first lithography technique, a second type of edges representing spacing that cannot be resolved by the second lithography technique but can be resolved by the first lithography technique; and
checking if there is a loop formed by odd number of vertices connected by edges of the first type.

### Claim 12 (depends on 11)

The method of claim 11, on condition that such loop exists, further comprising:
relocating at least one of the IC patterns corresponding to the vertices in the loop.

### Claim 13 (depends on 11)

The method of claim 11, on condition that such loop does not exist, further comprising:
identifying a first set of vertices that correspond to the IC patterns to be patterned by the first lithography technique.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
coloring the first set of vertices with a first color; and
coloring other vertices in the graph with the first color and a second color different from the first color, wherein two vertices directly connected by an edge of the first type are colored with different colors, and two vertices directly connected by an edge of the second type are colored with different colors or colored with the first color.

### Claim 15 (depends on 14)

The method of claim 14, after the coloring of other vertices, further comprising:
on condition that there are two vertices directly connected by an edge of the second type are colored with the second color, relocating at least one of the IC patterns corresponding to the two vertices in the IC layout.

### Claim 16

A method of fabricating an integrated circuit (IC) with a first lithography technique having a first resolution and a second lithography technique having a second resolution, the first resolution being finer than the second resolution, comprising:
receiving a layout of the IC, the layout having IC patterns;
deriving a graph from the layout, the graph having vertices and edges that connect some of the vertices, the vertices representing the IC patterns, the edges representing spacing between the IC patterns that are smaller than the second resolution;
classifying the edges into at least two types, a first type representing spacing that is smaller than the first resolution, a second type representing spacing that is equal to or greater than the first resolution but smaller than the second resolution; and
assigning two colors to all vertices that are connected by edges of the first type, wherein two vertices connected by a common edge of the first type are assigned with different colors.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
checking if there are two pairs of vertices in the graph such that the two pairs of vertices are connected through edges of the first type, a first pair of the two pairs are assigned with a first color and are connected directly by an edge of the second type, and a second pair of the two pairs are assigned with a second color different from the first color and are connected directly by another edge of the second type.

### Claim 18 (depends on 17)

The method of claim 17, on condition that such two pairs exist, further comprising:
modifying the IC layout with respect to the IC patterns corresponding to the two pairs.

### Claim 19 (depends on 17)

The method of claim 17, on condition that such two pairs do not exist, further comprising:
marking each pair of vertices that are assigned with a same color and are connected directly by an edge of the second type for patterning by the first lithography technique.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
marking other vertices in the graph for patterning by either the first lithography technique or the second lithography technique.