# US 10,483,119 B1 · Self-aligned double patterning (SADP) method

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- Number: US 10,483,119 B1
- Document ID: US10483119B1
- Status: Granted
- Kind: B1
- Application number: 16/161,421
- Filed: 2018-10-16
- Granted: 2019-11-19
- Earliest claimed: 2018-09-20
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jui-Yu Pan; Kuo-Chyuan Tzeng; Lee-Chuan Tseng; Ying-Hua Chen
- Web page: https://patentgrep.com/patent/US10483119B1

## CPC

- H10D 88/00: Three-dimensional [3D] integrated devices
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 88/01: {Manufacture or treatment}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present disclosure relates to integrated circuit device manufacturing processes. A self-aligned double patterning method is provided. In the method, a lithography process for line cut that determines the locations of line termini is performed after forming a spacer layer alongside the mandrel and prior to stripping the mandrel. The lithographic mask for the line cut is aligned to the mandrel and the spacer layer using a mark made of the mandrel material and the spacer material. Compared to the previous approach where the line cut process is performed after the mandrel removal, in the disclosed approach, the line termini mask is made of the mandrel material and the spacer material, and is more distinguishable compared to a mark made of just the spacer material. Thereby, the methods provide robust photo alignment signal for the line cut photolithography and precise positioning of the line termini mask.

## Claims

### Claim 1

A method of forming an integrated circuit device, comprising:
providing a substrate having a masking layer over the substrate and a sacrificial layer over the masking layer;
forming and patterning a first protection layer on the sacrificial layer;
patterning the sacrificial layer to form a plurality of mandrels and a mandrel mark next to the plurality of mandrels;
forming spacers along peripheries of the mandrels and the mandrel mark including along respective sides and ends of the mandrels;
forming a second protection layer to cover a first portion of the mandrels and the mandrel mark and to expose a second portion of the mandrels;
removing the exposed second portion of the mandrels and the spacers along respective sides and ends of the second portion of the mandrels;
removing the first portion of the mandrels while leaving the spacers along respective sides of the first portion of the mandrels;
forming a dummy protection layer next to the remaining spacers over a dummy region of the masking layer; and
patterning the masking layer according to the remaining spacers and the dummy protection layer to form a device mask, a dummy mask, and a mask level mark over the substrate.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a device layer over the substrate prior to forming the masking layer, wherein the masking layer is then formed on the device layer; and
patterning the device layer according to the device mask and the mask level mark to form a device structure and a device level mark structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plurality of mandrels and the mandrel mark are concurrently formed by a first photolithographic process that includes exposing and developing a first photoresist through a first lithographic mask and etching the sacrificial layer according to the developed first photoresist, wherein the first lithographic mask includes openings corresponding to the plurality of mandrels and the mandrel mark.

### Claim 4 (depends on 3)

The method of claim 3, wherein the second protection layer is formed by performing a second photolithographic process that includes exposing and developing a second photoresist through a second lithographic mask, wherein the second lithographic mask is aligned by locating the mandrel mark and corresponding portions of the spacers.

### Claim 5 (depends on 4)

The method of claim 4, wherein forming a second protection layer comprises forming a positive photoresist layer and patterning the positive photoresist layer using a second photolithographic mask.

### Claim 6 (depends on 4)

The method of claim 4, wherein the dummy protection layer is formed by performing a third photolithographic process that includes exposing and developing a third photoresist through a third lithographic mask.

### Claim 7 (depends on 6)

The method of claim 6, wherein the third lithographic mask is aligned to the remaining portions of the spacers.

### Claim 8 (depends on 1)

The method of claim 1, wherein the removing the first portion of the mandrels further comprises removing the mandrel mark together with the first portion of the mandrels.

### Claim 9 (depends on 1)

The method of claim 1, wherein the spacers are formed by depositing a spacer material followed by performing an anisotropic etch to the spacer material.

### Claim 10 (depends on 1)

The method of claim 1, wherein openings of the second protection layer determine endpoints of the device mask.

### Claim 11 (depends on 1)

The method of claim 1, wherein the masking layer is made of a first silicon nitride (SiN) layer, an amorphous carbon (APF) layer over the first SiN layer, and a second silicon nitride (SiN) layer over the APF layer.

### Claim 12 (depends on 1)

The method of claim 1, wherein the sacrificial layer is made of amorphous silicon, APF, ashing removable dielectric (ARD), or the combination thereof.

### Claim 13

A method of forming an integrated circuit device, comprising:
forming a masking layer over a substrate and a sacrificial layer over the masking layer;
patterning the sacrificial layer to form a plurality of mandrels and a mandrel mark next to the plurality of mandrels;
forming spacers along peripheries of the mandrels and the mandrel mark;
using the mandrel mark and the spacers along sides of the mandrel mark, performing a line cut process to remove a first portion of the mandrels and the spacers along sides of the first portion of the mandrels;
removing the remaining mandrels; and
patterning the masking layer according to the remaining spacers to form a device mask over the substrate.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
prior to patterning the masking layer, forming a dummy protection layer next to the remaining spacers over a dummy region of the masking layer, wherein the masking layer is patterned according to the dummy protection layer to form a dummy mask over the substrate.

### Claim 15 (depends on 13)

The method of claim 13, wherein the line cut process includes performing a second photolithographic process to protect selective portions of the spacers and mandrels from removal and removing unprotected portions of the spacers and mandrels, wherein the second photolithographic process is aligned by locating the mandrel mark and corresponding portions of the spacers.

### Claim 16 (depends on 15)

The method of claim 15,
wherein the second photolithographic process protects the mandrel mark and corresponding spacers from removal; and
wherein the mandrel mark is removed when removing the remaining mandrels.

### Claim 17 (depends on 16)

The method of claim 16, wherein patterning the masking layer also forms a mask level mark over the substrate together with the device mask.

### Claim 18 (depends on 13)

The method of claim 13,
wherein the mandrels have line-shaped features spaced one from another by gaps; and
wherein the mandrels and the gaps respectively have widths greater than that of the spacers.

### Claim 19

A method of forming an integrated circuit device, comprising:
forming a masking layer over a substrate;
forming a plurality of mandrels and a mandrel mark over the masking layer;
forming spacers along peripheries of the mandrels and the mandrel mark;
using the mandrel mark and the spacers along sides of the mandrel mark as an alignment marker, performing a photolithographic process to protect selective portions of the spacers and mandrels from removal and removing unprotected portions of the spacers and mandrels;
removing the remaining mandrels; and
patterning the masking layer according to the remaining spacers to form a device mask over the substrate.

### Claim 20 (depends on 19)

The method of claim 19, further comprising:
prior to patterning the masking layer, forming a dummy protection layer next to the remaining spacers over a dummy region of the masking layer, wherein the masking layer is patterned according to the dummy protection layer together with the remaining spacers to form a dummy mask together with a device mask over the substrate.