# US 10,483,115 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 10,483,115 B2
- Document ID: US10483115B2
- Status: Granted
- Kind: B2
- Application number: 15/692,528
- Filed: 2017-08-31
- Published: 2018-10-25
- Granted: 2019-11-19
- Earliest claimed: 2017-04-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: You-Hua Chou; Kuo-Sheng Chuang
- Web page: https://patentgrep.com/patent/US10483115B2

## CPC

- H10P 14/43: Chemical deposition, e.g. chemical vapour deposition [CVD]
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10K 85/221: {Carbon nanotubes}
- H10P 14/3406: {Carbon, e.g. diamond-like carbon}
- H10P 14/3464: {Nanotubes}
- H10P 14/6902: {composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]}
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4462: {Carbon or carbon-containing materials, e.g. graphene}
- H10W 20/4473: {Conductive organic materials, e.g. conductive adhesives or conductive inks}
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- B82Y 30/00: Nanotechnology for materials or surface science, e.g. nanocomposites
- H10W 20/0554: {of nanotubes or nanowires}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.

## Claims

### Claim 1

A semiconductor device, comprising:
a non-insulator structure formed in one of a source/drain region and a gate structure;
at least one carbon nano-tube (CNT) over the non-insulator structure;
a dielectric layer surrounding the CNT; and
a graphene-based conductive layer over the at least one CNT.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a conductive material filling interspaces between a plurality of the at least one CNTs.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the non-insulator structure comprises a metal silicide, and the metal silicide and the conductive material comprise the same metal.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising:
a catalyst layer between the at least one CNT and the non-insulator structure.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the catalyst layer and the non-insulator structure comprise the same metal.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a catalyst layer between the graphene-based conductive layer and the at least one CNT.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the catalyst layer wraps around the graphene-based conductive layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a conductor, wherein the graphene-based conductive layer wraps around the conductor.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein a top surface of the conductor is substantially level with an end surface of the graphene-based conductive layer.

### Claim 10

A semiconductor device, comprising:
a non-insulator structure;
a carbon nano-tube (CNT) electrically connected to the non-insulator structure;
a first dielectric layer, the CNT being within the first dielectric layer;
a second dielectric layer over the first dielectric layer; and
a U-shaped graphene-based conductive layer within the second dielectric layer and electrically connected to the CNT.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising:
a first catalyst layer; and
a second catalyst layer, wherein the CNT is in between the first catalyst layer and the second catalyst layer.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the CNT is in contact with the first catalyst layer.

### Claim 13 (depends on 11)

The semiconductor device of claim 11, wherein the U-shaped graphene-based conductive layer is in contact with the second catalyst layer.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, further comprising:
a metal wrapping around the CNT.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, further comprising:
a metal, wherein the U-shaped graphene-based conductive layer is disposed on sidewalls and a bottom surface of the metal.

### Claim 16

A method for manufacturing a semiconductor device, comprising:
forming a hole in a first dielectric layer over a non-insulator structure;
forming a carbon nano-tube (CNT) in the hole and electrically connected to the non-insulator structure;
forming a second dielectric layer over the CNT and the first dielectric layer;
forming a trench in the second dielectric layer and exposing a top surface of the CNT; and
after forming the trench, forming a graphene-based conductive layer in the trench and electrically connected to the CNT.

### Claim 17 (depends on 16)

The method of claim 16, wherein the forming the CNT comprises:
forming a catalyst layer in the hole; and
growing the CNT over the catalyst layer.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
filling the hole with a metal after the forming the CNT.

### Claim 19 (depends on 16)

The method of claim 16, wherein the forming the graphene-based conductive layer comprises:
forming a catalyst layer in the trench; and
growing the graphene-based conductive layer over the catalyst layer.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
filling the trench with a metal after the forming the graphene-based conductive layer.