# US 10,483,105 B2 · Nanowire bending for planar device process on (001) Si substrates > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,105 B2 - Document ID: US10483105B2 - Status: Granted - Kind: B2 - Application number: 15/573,772 - Filed: 2016-05-13 - Published: 2018-12-13 - Granted: 2019-11-19 - Earliest claimed: 2015-05-13 - Assignees: Stc.Unm - Applicants: Stc.Unm - Inventors: Seung-Chang Lee; Steven R. J. Brueck - Web page: https://patentgrep.com/patent/US10483105B2 ## CPC - H10P 14/38: {characterised by treatments done after the formation of the materials} - B81C 1/00111: {Tips, pillars, i.e. raised structures (microneedles A61M37/0015)} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/031: {of thin-film transistors [TFT]} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)} - H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 62/121: {oriented parallel to substrates} - H10D 84/0167: {Manufacturing their channels} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10P 14/271: {characterised by the preparation of substrate for selective deposition} - H10P 14/274: {using seed materials} - H10P 14/279: {Vapour-liquid-solid growth} - H10P 14/2905: {Silicon, silicon germanium or germanium} - H10P 14/2926: {Crystal orientations} - H10P 14/3411: {Silicon, silicon germanium or germanium} - H10P 14/3412: {including tin} - H10P 14/3421: {Arsenides} - H10P 14/3462: {Nanowires} - H10P 14/44: Physical vapour deposition [PVD] - H10P 14/6308: {of Group IV semiconductors} - H10P 50/283: {by chemical means} - H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)} - B82Y 40/00: Manufacture or treatment of nanostructures - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract Provided is a method for growing a nanowire, including: providing a substrate with a base portion having a first surface and at least one support structure extending above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending from the root end; and elastically bending the at least one nanowire. ## Claims ### Claim 1 A method for growing a nanowire, comprising: providing a substrate comprising a base portion having a first surface and at least one support structure extending either above or below the first surface; forming a dielectric coating on the at least one support structure; forming a photoresist coating over the substrate, wherein the photoresist coating surrounds a portion of the at least one support structure; forming a metal coating over at least a portion of the dielectric coating; removing a portion of the dielectric coating to expose a surface of the at least one support structure; removing a portion of the at least one support structure to form a nanowire growth surface; growing at least one nanowire on the nanowire growth surface of a corresponding one of the at least one support structure, wherein the nanowire comprises a root end attached to the growth surface and an opposing, free end extending away from the support structure; and elastically bending the at least one nanowire. ### Claim 2 (depends on 1) The method of claim 1, wherein the support structure comprises a crystallographic extension of the substrate. ### Claim 3 (depends on 1) The method of claim 1, wherein the support structure comprises Si. ### Claim 4 (depends on 1) The method of claim 1, wherein forming the dielectric coating comprises thermally oxidizing a surface of the support structure. ### Claim 5 (depends on 1) The method of claim 1, wherein the dielectric coating comprises SiO2 or SiNx. ### Claim 6 (depends on 1) The method of claim 1, wherein forming the metal coating comprises double deposition of a metal by e-beam evaporation over the dielectric coating with the substrate rotated from a normal of the e-beam axis to provide a shadow coverage. ### Claim 7 (depends on 6) The method of claim 6, wherein the metal coating includes a discontinuity comprising an opening through which the dielectric coating is exposed. ### Claim 8 (depends on 7) The method of claim 7, wherein the removing at least a portion of the dielectric coating comprises removing the portion of the dielectric coating exposed by the opening. ### Claim 9 (depends on 7) The method of claim 7, wherein the opening is oriented parallel to a <110>direction of the substrate, such that a selective etching of at least a portion of the support structure to form the nanowire growth surface comprises using a facet selective etching process to form a (111) face on a surface of the support structure. ### Claim 10 (depends on 7) The method of claim 7, wherein the removing at least a portion of the dielectric coating comprises dry etching the portion of the dielectric coating exposed by the opening. ### Claim 11 (depends on 1) The method of claim 1, wherein the removing of a portion of the support structure comprises forming a single (111) facet by anisotropic wet etching of the support structure with a wet etchant. ### Claim 12 (depends on 1) The method of claim 1, wherein elastically bending the at least one nanowire comprises manipulating the nanowire such that at least a portion of a length of the nanowire is made to contact a surface of the substrate. ### Claim 13 (depends on 1) The method of claim 1, wherein the metal coating comprises Cr. ### Claim 14 (depends on 1) The method of claim 1, wherein the at least one support structure comprises an array of support structures, wherein the at least one nanowire comprises an array of nanowires, wherein at least one nanowire of the array of nanowires is grown on a corresponding one of the array of support structures. ### Claim 15 (depends on 1) The method of claim 1, further comprising: fully covering the nanowire in a second photoresist; forcing at least a portion of a nanoimprint stamp through the second photoresist so that the nanoimprint stamp comes into contact with the nanowire; manipulating the nanowire with the nanoimprint stamp such that it contacts a step portion of the substrate; removing the nanoimprint stamp from the second photoresist, wherein forcing of at least a portion of the nanoimprint stamp through the second photoresist forms at least one slot that extends through the photoresist to the nanowire; and depositing a polymer through the at least one slot onto the nanowire, wherein the polymer anchors the nanowire to a surface of the substrate. ### Claim 16 (depends on 15) The method of claim 15, wherein the photoresist coating is formed on a portion of the dielectric coating except at a top portion of the support structure, and wherein the metal coating is formed on the dielectric coating at the top portion of the support structure. ### Claim 17 (depends on 1) The method of claim 1, wherein the forming of the metal coating is performed before the forming of the photoresist coating and comprises fully covering the support structure with the metal coating. ### Claim 18 (depends on 17) The method of claim 17, wherein the forming of the photoresist coating comprises fully covering the support structure with photoresist and removing a portion of the photoresist coating to expose a top portion of the support structure. ### Claim 19 (depends on 18) The method of claim 18, further comprising removing a portion of the metal coating at a top portion of the support structure to expose a portion of the dielectric coating formed on the top portion of the support structure. ### Claim 20 (depends on 19) The method of claim 19, further comprising forming a second metal coating over the dielectric coating formed on the top portion of the support structure, wherein the second metal coating and the metal coating comprise the same metal.