# US 10,483,085 B2 · Use of ion beam etching to generate gate-all-around structure

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- Number: US 10,483,085 B2
- Document ID: US10483085B2
- Status: Granted
- Kind: B2
- Application number: 15/351,882
- Filed: 2016-11-15
- Published: 2017-03-02
- Granted: 2019-11-19
- Earliest claimed: 2014-10-21
- Assignees: Lam Research Corporation
- Applicants: Lam Research Corporation
- Inventors: Ivan L. Berry, III; Thorsten Lill
- Web page: https://patentgrep.com/patent/US10483085B2

## CPC

- H01J 37/3023: {Program control}
- H01J 37/3056: {for microworking, e. g. etching of gratings or trimming of electrical components}
- H01J 37/32422: {Arrangement for selecting ions or species in the plasma}
- H01J 37/32752: {for moving the material across the discharge}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/435: {having multiple laterally adjacent 1D material channels}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10P 50/242: {of Group IV materials}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10P 72/0421: {for drying etching}
- H01J 2237/202: Movement
- H01J 2237/30472: Controlling the beam
- H01J 2237/3151: Etching
- H01J 2237/3174: Etching microareas
- H01J 2237/3341: Reactive etching
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Various embodiments herein relate to methods and apparatus for performing anisotropic ion beam etching to form arrays of channels. The channels may be formed in semiconductor material, and may be used in a gate-all-around device. Generally speaking, a patterned mask layer is provided over a layer of semiconductor material. Ions are directed toward the substrate while the substrate is positioned in two particular orientations with respect to the ion trajectory. The substrate switches between these orientations such that ions impinge upon the substrate from two opposite angles. The patterned mask layer shadows/protects the underlying semiconductor material such that the channels are formed in intersecting shadowed regions.

## Claims

### Claim 1

A method of forming channels or nanowires for a gate-all-around device or other electronic device, the method comprising:
(a) providing a substrate on a substrate holder in a reaction chamber, the substrate comprising a patterned mask layer over semiconductor material, wherein the patterned mask layer comprises a plurality of linear mask portions oriented substantially parallel to one another;
(b) orienting the substrate with respect to an ion trajectory in a first orientation and directing ions toward the substrate in a first direction, the plurality of linear mask portions protecting a plurality of first shadowed regions, wherein the ions impact the substrate at a first incidence angle to thereby etch the semiconductor material to form a first set of trenches between adjacent first shadowed regions;
(c) orienting the substrate with respect to the ion trajectory in a second orientation and directing the ions toward the substrate in a second direction, the plurality of linear mask portions protecting a plurality of second shadowed regions, wherein the ions impact the substrate at a second incidence angle to thereby etch the semiconductor material to form a second set of trenches between adjacent second shadowed regions;
(d) repeating (b)-(c) to further etch the first and second sets of trenches, wherein the first and second set of trenches intersect with one another, wherein the first shadowed regions and second shadowed regions intersect with one another, and wherein the channels or nanowires are formed in a direction parallel to the plurality of linear mask portions, in areas where the first and second shadowed regions intersect with one another.

### Claim 2 (depends on 1)

The method of claim 1, wherein orienting the substrate with respect to the ion trajectory in (b) and/or (c) comprises (i) orienting the substrate, and/or (ii) orienting the ion trajectory.

### Claim 3 (depends on 1)

The method of claim 1, wherein the channels or nanowires are formed in an array comprising two or more rows of channels or nanowires, each row comprising two or more channels or nanowires.

### Claim 4 (depends on 1)

The method of claim 1, further comprising translating the substrate while directing ions toward the substrate in (b) and/or (c).

### Claim 5 (depends on 1)

The method of claim 1, wherein the ions are delivered in the form of a plurality of ion beams that have a divergence of about 1° or less, and wherein an array of channels or nanowires is formed, the array comprising at least three rows of channels or nanowires.

### Claim 6 (depends on 1)

The method of claim 1, further comprising after (d), etching the channels or nanowires to make the channels or nanowires more round.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming the gate-all-around device, wherein the channels or nanowires formed in (a)-(c) are channels or nanowires in the gate-all-around device.

### Claim 8 (depends on 1)

The method of claim 1, wherein the orientation of the substrate with respect to the ion trajectory is switched at least 2 times during formation of the channels or nanowires.