# US 10,483,055 B2 · Programmable arc fault circuit interrupter (AFCI) > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,483,055 B2 - Document ID: US10483055B2 - Status: Granted - Kind: B2 - Application number: 15/643,293 - Filed: 2017-07-06 - Published: 2018-05-31 - Granted: 2019-11-19 - Earliest claimed: 2016-11-26 - Assignees: Tower Manufacturing Corporation - Applicants: Victor V. Aromin; David Durfee; Petar Horvatic; Steven O'Connell - Inventors: Victor V. Aromin; David Durfee; Petar Horvatic; Steven O'Connell - Web page: https://patentgrep.com/patent/US10483055B2 ## CPC - G01R 31/52: Testing for short-circuits, leakage current or ground faults - G01R 31/14: Circuits therefor {, e.g. for generating test voltages, sensing circuits (G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327)} - H01H 9/50: Means for detecting the presence of an arc or discharge - H01H 9/54: Circuit arrangements not adapted to a particular application of the switching device and for which no provision exists elsewhere - H02H 1/0015: {Using arc detectors} - H02H 3/08: responsive to excess current (responsive to abnormal temperature caused by excess current H02H5/04) - G01R 19/2509: {Details concerning sampling, digitizing or waveform capturing} - G01R 19/2513: {Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging} - H01H 2083/201: {the other abnormal electrical condition being an arc fault} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H01H: ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES (contact cables H01B7/10; electrolytic self-interrupters H01G9/18; emergency protective circuit arrangements H02H; switching by electronic means without contact-making H03K17/00) - H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H) ## Abstract A programmable arc fault circuit interrupter (AFCI) is provided. The programmable AFCI includes a dual resistive shunt array for developing inputs to an analog front end which in turn develops trigger quantities for input to a programmable processor. The programmable processor determines if the trigger quantities, singularly, or in the aggregate, exceed predetermined thresholds. Determining the predetermined thresholds are exceeded the processor issues a trigger command to momentarily energize a delatching coil, thus removing AC mains power from a load. ## Claims ### Claim 1 A programmable Arc Fault Circuit Interrupter (PAFCI) for disengaging alternating current (AC) power from a load, the PAFCI comprising: a relay switch disposed between the AC power and the load; a trigger circuit for actuating the relay switch; a plurality of sensing devices disposed between the AC power and the load; at least one sensing circuit connectable to the plurality of sensing devices, wherein the sensing circuit determines at least one circuit parameter; and a processor circuit connectable to the trigger circuit, wherein the processor circuit determines from the at least one circuit parameter if an arcing condition exists; and wherein the PAFCI does not include toroidal devices for sensing arcing conditions. ### Claim 2 (depends on 1) The PAFCI as in claim 1 wherein the plurality of sensing devices comprises a plurality of resistors connected in series. ### Claim 3 (depends on 1) The PAFCI as in claim 1 further comprising a power supply circuit connectable to the at least one sensing circuit, wherein the power supply circuit comprises a capacitive power supply. ### Claim 4 (depends on 3) The PAFCI as in claim 3, wherein the capacitive power supply comprises a low drop out (LDO) regulator. ### Claim 5 (depends on 1) The PAFCI as in claim 1 wherein the at least one sensing circuit comprises: a voltage sense circuit, wherein the voltage sense circuit determines a first circuit parameter (AIN_V); and a voltage zero crossing detection circuit (ZCD), wherein the voltage ZCD determines a second circuit parameter (AIN_ZCD). ### Claim 6 (depends on 1) The PAFCI as in claim 1 wherein the at least one sensing circuit comprises: a main current shunt circuit, wherein the main current shunt circuit determines a third circuit parameter (AIN_I); and a small current shunt circuit, wherein the small current shunt circuit determines, a fourth circuit parameter (AIN_I2). ### Claim 7 (depends on 6) The PAFCI as in claim 6, wherein the processor circuit comprises microcontroller, wherein the microcontroller comprises a non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a program of instructions executable by the microcontroller to calibrate the main current shunt circuit. ### Claim 8 (depends on 1) The PAFCI as in claim 1, wherein the processor circuit comprises a microcontroller, wherein the microcontroller comprises: a non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a program of instructions executable by the microcontroller to determine an inrush/power-on arc condition or a steady state arc condition. ### Claim 9 (depends on 1) The PAFCI as in claim 1, wherein the processor circuit comprises a microcontroller, wherein the microcontroller comprises: a non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a program of instructions executable by the microcontroller to determine: CLVinst=instantaneous Current leads voltage in units of samples; FSWinst=Instantaneous Flat Spot Width in units of samples; CLVflt=low Pass Filtered CLVinst in units of samples; FSWflt=Low Pass Filtered FSWinst in units of samples; CLV′flt=low Pass Filtered CLVinst Variance; FSW′flt=low Pass Filtered FSW Variance; CLV″flt=CLV′inst−CLV′flt; and FSW″flt=Low Pass Filtered Derivative of FSW Variance. ### Claim 10 (depends on 9) The PAFCI as in claim 9, wherein the processor circuit comprises the microcontroller, wherein determining the inrush/power-on arc condition further comprises the non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies the program of instructions executable by the microcontroller to determine the inrush/power-on arcing condition, wherein the instructions include: incrementing a first event counter if CLfl pk is less than a predetermined maximum and CLVflt is greater than a predetermined first inrush sample quantity and if FSW′flt is less than a predetermined second inrush sample quantity; and triggering the trigger circuit if the first event counter exceeds a predetermined event count. ### Claim 11 (depends on 9) The PAFCI as in claim 9, wherein the processor circuit comprises the microcontroller, wherein determining the inrush/power-on arc condition further comprises the non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies the program of instructions executable by the microcontroller to determine the steady state (SS) arcing condition, wherein the instructions include: incrementing a second event counter: if CLVflt>SS1 AND SS2>FSW″flt>SS3 AND SS4>CLV″flt>SS5; or if CLVflt>SS1 AND SS2>FSW″flt>SS6 AND SS7>CLV″flt>SS3 AND T>T1 sec; or if CLVflt>SS8 AND FSWflt>SS9 AND FSW″flt>SS10 AND CLV″flt>SS11 AND T>T1 sec; where SS1, SS2, SS3, SS4, SS5, SS6, SS7, SS8, SS9, SS10, SS11=steady state arcing parameters; and triggering the trigger circuit if the second event counter exceeds a predetermined event count. ### Claim 12 A programmable Arc Fault Circuit Interrupter (PAFCI) for classifying arcing parameters according to a connected load and detecting parallel or series arcing in accordance with the arcing parameters, the PAFCI comprising: a sensing circuit; a processor circuit connectable to the sensing circuit, wherein the processor circuit comprises: a microcontroller, wherein the microcontroller comprises: a non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a first program of instructions executable by the microcontroller to classify the arcing parameters according to the connected load; a non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a second program of instructions executable by the microcontroller to determine a parallel arcing condition; the non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a third program of instructions executable by the microcontroller to determine a series arcing condition; and wherein the PAFCI does not include toroidal devices for sensing series or parallel arcing conditions. ### Claim 13 (depends on 12) The PAFCI as in claim 12 further comprising a non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a program of instructions executable by the microcontroller to determine CLVinst=instantaneous Current leads voltage. ### Claim 14 (depends on 12) The PAFCI as in claim 12 wherein the sensing circuit comprises: a main current shunt analog-digital-converter (ADC) circuit, wherein the main current shunt ADC circuit determines a first circuit parameter (AIN_I); a small current shunt ADC circuit, wherein the small current shunt ADC circuit determines a second circuit parameter (AIN_I2); and wherein the first and second circuit parameters are processed by the microcontroller to determine a parallel arcing condition. ### Claim 15 (depends on 12) The PAFCI as in claim 12 wherein the at least one sensing circuit comprises: a voltage sense circuit, wherein the voltage sense circuit determines a third circuit parameter (AIN_V); and a voltage zero crossing detection circuit (ZCD), wherein the voltage ZCD determines a fourth circuit parameter (AIN_ZCD). ### Claim 16 A method for detecting arc faults based upon connected load dependent arcing threshold parameters, the method comprising: classifying the dependent arcing threshold parameters according to the connected load and wherein classifying the dependent arcing threshold parameters according to the connected load further comprises: determining the following circuit parameters according to the connected load; CLVinst=instantaneous Current leads voltage in units of samples; FSWinst=Instantaneous Flat Spot Width in units of samples; CLVflt=low Pass Filtered CLVinst in units of samples; FSWflt=Low Pass Filtered FSWinst in units of samples; CLV′flt=low Pass Filtered CLVinst Variance; FSW′flt=low Pass Filtered FSW Variance; CLV″flt=CLV′inst−CLV′flt; and FSW″flt=Low Pass Filtered Derivative of FSW Variance; and determining if an arcing condition exists based upon the dependent arcing threshold parameters. ### Claim 17 (depends on 16) The method as in claim 16 wherein determining CLVinst further comprises: determining a half current cycle associated with the connected load; determining the beginning of the FSWinst; determining a voltage zero (ZC) crossing; determining the end of the FSWinst; and calculating CLVinst from the beginning of the FSWinst to the ZC crossing at the end of the FSWinst. ### Claim 18 (depends on 16) The method as in claim 16 wherein determining CLVinst further comprises: determining a full current cycle associated with the connected load; determining the beginning of the FSWinst; determining a voltage zero (ZC) crossing before the beginning of the FSWinst; determining the end of the FSWinst; and calculating CLVinst from the beginning of the FSWinst to the ZC crossing at the end of the FSWinst. ### Claim 19 (depends on 16) The method as in claim 16 wherein classifying the dependent arcing threshold parameters according to the connected load further comprises: providing a processor circuit, wherein the processor circuit comprises: a microcontroller, wherein the microcontroller comprises: a non-transitory program storage medium readable by the microcontroller, wherein the program storage medium tangibly embodies a first program of instructions executable by the microcontroller to classify the arcing parameters according to the connected load.